From: Christopher Celio <celio@eecs.berkeley.edu>
Date: Tue, 21 Jul 2015 19:45:17 +0000 (-0700)
Subject: Update README.md for freg info
X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=092f378fb207d9378118c8b39c90f2b45833c862

Update README.md for freg info
---

diff --git a/README.md b/README.md
index eabd355..ce078b3 100644
--- a/README.md
+++ b/README.md
@@ -64,9 +64,19 @@ To invoke interactive debug mode, launch spike with -d:
 
     $ spike -d pk hello
 
-To see the contents of a register (0 is for core 0):
+To see the contents of an integer register (0 is for core 0):
 
     : reg 0 a0
+    
+To see the contents of a floating point register:
+
+    : fregs 0 ft0
+    
+or:
+  
+    : fregd 0 ft0
+    
+depending upon whether you wish to print the register as single- or double-precision.
 
 To see the contents of a memory location (physical address in hex):