From: Tim Newsome <tim@sifive.com>
Date: Thu, 8 Jun 2017 20:05:01 +0000 (-0700)
Subject: Reset to "success" instead of "error."
X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=1a904654f1d7e6ea5f43f8d0039fadebd9c1aa88

Reset to "success" instead of "error."

OpenOCD actually checks this initial value now, and there's no reason
for it to indicate error.
---

diff --git a/riscv/jtag_dtm.cc b/riscv/jtag_dtm.cc
index cd3f3ee..3a0e8d2 100644
--- a/riscv/jtag_dtm.cc
+++ b/riscv/jtag_dtm.cc
@@ -41,7 +41,7 @@ jtag_dtm_t::jtag_dtm_t(debug_module_t *dm) :
   dm(dm),
   _tck(false), _tms(false), _tdi(false), _tdo(false),
   dtmcontrol((abits << DTM_DTMCS_ABITS_OFFSET) | 1),
-  dmi(DMI_OP_STATUS_FAILED << DTM_DMI_OP_OFFSET),
+  dmi(DMI_OP_STATUS_SUCCESS << DTM_DMI_OP_OFFSET),
   _state(TEST_LOGIC_RESET)
 {
 }