From: Tim Newsome <tim@sifive.com>
Date: Mon, 25 Sep 2017 18:05:36 +0000 (-0700)
Subject: Merge pull request #128 from riscv/reset
X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=58b6c187df1a5cc066c97a63483d297fd159f241

Merge pull request #128 from riscv/reset

Fix debug reset.
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58b6c187df1a5cc066c97a63483d297fd159f241