From: Christopher Celio Date: Fri, 15 Aug 2014 22:38:41 +0000 (-0700) Subject: Added PC histogram option. X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=616cc32c30ac0684edfd50ed44fc78ed1bc20884 Added PC histogram option. - Spits out all PCs (on 4B granularity) executed with count. - Requires a compile time configuration option. - Also requires a run-time flag. --- diff --git a/config.h.in b/config.h.in index 4ea8c5e..42d4d22 100644 --- a/config.h.in +++ b/config.h.in @@ -42,6 +42,9 @@ /* Define if floating-point instructions are supported */ #undef RISCV_ENABLE_FPU +/* Enable PC histogram generation */ +#undef RISCV_ENABLE_HISTOGRAM + /* Define if subproject MCPPBS_SPROJ_NORM is enabled */ #undef SOFTFLOAT_ENABLED diff --git a/configure b/configure index 4a1bf3d..6eae9bf 100755 --- a/configure +++ b/configure @@ -650,6 +650,7 @@ with_fesvr enable_fpu enable_64bit enable_commitlog +enable_histogram ' ac_precious_vars='build_alias host_alias @@ -1286,6 +1287,7 @@ Optional Features: --disable-fpu Disable floating-point --disable-64bit Disable 64-bit mode --enable-commitlog Enable commit log generation + --enable-histogram Enable PC histogram generation Optional Packages: --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] @@ -4214,6 +4216,19 @@ if test "x$enable_commitlog" = "xyes"; then : $as_echo "#define RISCV_ENABLE_COMMITLOG /**/" >>confdefs.h +fi + +# Check whether --enable-histogram was given. +if test "${enable_histogram+set}" = set; then : + enableval=$enable_histogram; +fi + +if test "x$enable_histogram" = "xyes"; then : + + +$as_echo "#define RISCV_ENABLE_HISTOGRAM /**/" >>confdefs.h + + fi diff --git a/riscv/processor.cc b/riscv/processor.cc index 4b282f6..0a2d266 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -35,6 +35,16 @@ processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id) processor_t::~processor_t() { +#ifdef RISCV_ENABLE_HISTOGRAM + if (histogram_enabled) + { + fprintf(stderr, "PC Histogram size:%lu\n", pc_histogram.size()); + for(auto iterator = pc_histogram.begin(); iterator != pc_histogram.end(); ++iterator) { + fprintf(stderr, "%0lx %lu\n", (iterator->first << 2), iterator->second); + } + } +#endif + delete disassembler; } @@ -75,6 +85,11 @@ void processor_t::set_debug(bool value) ext->set_debug(value); } +void processor_t::set_histogram(bool value) +{ + histogram_enabled = value; +} + void processor_t::reset(bool value) { if (run == !value) @@ -118,10 +133,19 @@ static void commit_log(state_t* state, insn_t insn) #endif } +inline void processor_t::update_histogram(size_t pc) +{ +#ifdef RISCV_ENABLE_HISTOGRAM + size_t idx = pc >> 2; + pc_histogram[idx]++; +#endif +} + static inline void execute_insn(processor_t* p, state_t* st, insn_fetch_t fetch) { reg_t npc = fetch.func(p, fetch.insn.insn, st->pc); commit_log(st, fetch.insn.insn); + p->update_histogram(st->pc); st->pc = npc; } diff --git a/riscv/processor.h b/riscv/processor.h index 41268f9..58c31cb 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -6,6 +6,7 @@ #include "config.h" #include #include +#include class processor_t; class mmu_t; @@ -69,6 +70,7 @@ public: ~processor_t(); void set_debug(bool value); + void set_histogram(bool value); void reset(bool value); void step(size_t n); // run for n cycles void deliver_ipi(); // register an interprocessor interrupt @@ -81,6 +83,7 @@ public: state_t* get_state() { return &state; } extension_t* get_extension() { return ext; } void yield_load_reservation() { state.load_reservation = (reg_t)-1; } + void update_histogram(size_t pc); void register_insn(insn_desc_t); void register_extension(extension_t*); @@ -94,11 +97,13 @@ private: uint32_t id; bool run; // !reset bool debug; + bool histogram_enabled; bool rv64; std::vector instructions; std::vector opcode_map; std::vector opcode_store; + std::map pc_histogram; void take_interrupt(); // take a trap if any interrupts are pending void take_trap(trap_t& t); // take an exception diff --git a/riscv/riscv.ac b/riscv/riscv.ac index a65039b..4076dc3 100644 --- a/riscv/riscv.ac +++ b/riscv/riscv.ac @@ -25,3 +25,8 @@ AC_ARG_ENABLE([commitlog], AS_HELP_STRING([--enable-commitlog], [Enable commit l AS_IF([test "x$enable_commitlog" = "xyes"], [ AC_DEFINE([RISCV_ENABLE_COMMITLOG],,[Enable commit log generation]) ]) + +AC_ARG_ENABLE([histogram], AS_HELP_STRING([--enable-histogram], [Enable PC histogram generation])) +AS_IF([test "x$enable_histogram" = "xyes"], [ + AC_DEFINE([RISCV_ENABLE_HISTOGRAM],,[Enable PC histogram generation]) +]) diff --git a/riscv/sim.cc b/riscv/sim.cc index 59fe593..9490af3 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -40,8 +40,10 @@ sim_t::sim_t(size_t nprocs, size_t mem_mb, const std::vector& args) debug_mmu = new mmu_t(mem, memsz); - for (size_t i = 0; i < procs.size(); i++) + for (size_t i = 0; i < procs.size(); i++) { procs[i] = new processor_t(this, new mmu_t(mem, memsz), i); + } + } sim_t::~sim_t() @@ -124,8 +126,17 @@ void sim_t::set_debug(bool value) debug = value; } +void sim_t::set_histogram(bool value) +{ + histogram_enabled = value; + for (size_t i = 0; i < procs.size(); i++) { + procs[i]->set_histogram(histogram_enabled); + } +} + void sim_t::set_procs_debug(bool value) { for (size_t i=0; i< procs.size(); i++) procs[i]->set_debug(value); } + diff --git a/riscv/sim.h b/riscv/sim.h index d437c1a..9e1362e 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -23,6 +23,7 @@ public: bool running(); void stop(); void set_debug(bool value); + void set_histogram(bool value); void set_procs_debug(bool value); htif_isasim_t* get_htif() { return htif.get(); } @@ -48,6 +49,7 @@ private: size_t current_step; size_t current_proc; bool debug; + bool histogram_enabled; // provide a histogram of PCs // presents a prompt for introspection into the simulation void interactive(); diff --git a/spike/spike.cc b/spike/spike.cc index c8b4d7c..5c8901c 100644 --- a/spike/spike.cc +++ b/spike/spike.cc @@ -20,6 +20,7 @@ static void help() fprintf(stderr, " -p Simulate processors\n"); fprintf(stderr, " -m Provide MB of target memory\n"); fprintf(stderr, " -d Interactive debug mode\n"); + fprintf(stderr, " -g Track histogram of PCs\n"); fprintf(stderr, " -h Print this help message\n"); fprintf(stderr, " --ic=:: Instantiate a cache model with S sets,\n"); fprintf(stderr, " --dc=:: W ways, and B-byte blocks (with S and\n"); @@ -32,6 +33,7 @@ static void help() int main(int argc, char** argv) { bool debug = false; + bool histogram = false; size_t nprocs = 1; size_t mem_mb = 0; std::unique_ptr ic; @@ -43,6 +45,7 @@ int main(int argc, char** argv) parser.help(&help); parser.option('h', 0, 0, [&](const char* s){help();}); parser.option('d', 0, 0, [&](const char* s){debug = true;}); + parser.option('g', 0, 0, [&](const char* s){histogram = true;}); parser.option('p', 0, 1, [&](const char* s){nprocs = atoi(s);}); parser.option('m', 0, 1, [&](const char* s){mem_mb = atoi(s);}); parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));}); @@ -77,5 +80,6 @@ int main(int argc, char** argv) } s.set_debug(debug); + s.set_histogram(histogram); return s.run(); }