From: Wesley W. Terpstra <wesley@sifive.com>
Date: Wed, 22 Mar 2017 03:53:09 +0000 (-0700)
Subject: sim: declare cores as interrupt-controllers for clint
X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=693fc45eb8ccc3c9f84b898de3119a172e0776f5

sim: declare cores as interrupt-controllers for clint
---

diff --git a/riscv/sim.cc b/riscv/sim.cc
index a2b5cd1..bdf55e2 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -276,6 +276,8 @@ void sim_t::make_dtb()
          "      riscv,isa = \"" << procs[i]->isa_string << "\";\n"
          "      mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
          "      clock-frequency = <" << CPU_HZ << ">;\n"
+         "      interrupt-controller;\n"
+         "      #interrupt-cells = <1>;\n"
          "    };\n";
   }
   reg_t membs = DRAM_BASE;