From: Andrew Waterman <andrew@sifive.com>
Date: Wed, 3 Jan 2018 21:06:21 +0000 (-0800)
Subject: Add some missing RVC instructions to disassembler
X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=874e55888f23024899db93231d2b7c672fab33bb

Add some missing RVC instructions to disassembler
---

diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc
index 49f4de2..982064d 100644
--- a/spike_main/disasm.cc
+++ b/spike_main/disasm.cc
@@ -545,6 +545,9 @@ disassembler_t::disassembler_t(int xlen)
   DISASM_INSN("lui", c_lui, 0, {&xrd, &rvc_uimm});
   DISASM_INSN("addi", c_addi, 0, {&xrd, &xrd, &rvc_imm});
   DISASM_INSN("slli", c_slli, 0, {&xrd, &rvc_shamt});
+  DISASM_INSN("srli", c_srli, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_shamt});
+  DISASM_INSN("srai", c_srai, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_shamt});
+  DISASM_INSN("andi", c_andi, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_imm});
   DISASM_INSN("mv", c_mv, 0, {&xrd, &rvc_rs2});
   DISASM_INSN("add", c_add, 0, {&xrd, &xrd, &rvc_rs2});
   DISASM_INSN("addw", c_addw, 0, {&rvc_rs1s, &rvc_rs1s, &rvc_rs2s});