From: Megan Wachs <megan@sifive.com>
Date: Tue, 18 Apr 2017 18:44:00 +0000 (-0700)
Subject: debug: Add fence and fence.i to ensure Debug RAM is ready.
X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=91baeee2d89714cc2ea23806a98528e1e4b5da6a

debug: Add fence and fence.i to ensure Debug RAM is ready.
---

diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index 83108e2..2ee7a31 100755
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -1,22 +1,7 @@
 // See LICENSE.SiFive for license details.
 
 #include "spike/encoding.h"
-
-// These are implementation-specific addresses in the Debug Module
-#define DEBUG_ROM_HALTED    0x100
-#define DEBUG_ROM_GOING     0x104
-#define DEBUG_ROM_RESUMING  0x108
-#define DEBUG_ROM_EXCEPTION 0x10C
-
-// Region of memory where each hart has 1
-// byte to read.
-#define DEBUG_ROM_FLAGS 0x400
-#define DEBUG_ROM_FLAG_GO     0
-#define DEBUG_ROM_FLAG_RESUME 1
-
-// These needs to match the link.ld         
-#define DEBUG_ROM_WHERETO 0x300
-#define DEBUG_ROM_ENTRY   0x800
+#include "debug_rom_defines.h"
         
         .option norvc
         .global entry
@@ -60,12 +45,14 @@ _exception:
         ebreak
 
 going:
-        csrr s0, CSR_DSCRATCH          // Restore s0 here
-        sw zero, DEBUG_ROM_GOING(zero)           // When debug module sees this write, the GO flag is reset.
-        jalr zero, zero, %lo(whereto)          // Rocket-Chip has a specific hack which is that jalr in
-                                       // Debug Mode will flush the I-Cache. We need that so that the
-                                       // remainder of the variable instructions will be what Debug Module
-                                       // intends.
+        csrr s0, CSR_DSCRATCH            // Restore s0 here
+        sw zero, DEBUG_ROM_GOING(zero)   // When debug module sees this write, the GO flag is reset.
+        fence
+        fence.i
+        jalr zero, zero, %lo(whereto)    // Debug module will put different instructions and data in the RAM, 
+                                         // so we use fence and fence.i for safety. (rocket-chip doesn't have this
+                                         // because jalr is special there)
+
 _resume:
         csrr s0, CSR_MHARTID
         sw   s0, DEBUG_ROM_RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset.
diff --git a/debug_rom/debug_rom.h b/debug_rom/debug_rom.h
index f389bf8..d21e166 100644
--- a/debug_rom/debug_rom.h
+++ b/debug_rom/debug_rom.h
@@ -1,11 +1,12 @@
 static const unsigned char debug_rom_raw[] = {
-  0x6f, 0x00, 0xc0, 0x00, 0x6f, 0x00, 0xc0, 0x04, 0x6f, 0x00, 0x40, 0x03,
+  0x6f, 0x00, 0xc0, 0x00, 0x6f, 0x00, 0x40, 0x05, 0x6f, 0x00, 0x40, 0x03,
   0x0f, 0x00, 0xf0, 0x0f, 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x40, 0xf1,
   0x23, 0x20, 0x80, 0x10, 0x03, 0x44, 0x04, 0x40, 0x13, 0x74, 0x14, 0x00,
   0x63, 0x10, 0x04, 0x02, 0x73, 0x24, 0x40, 0xf1, 0x03, 0x44, 0x04, 0x40,
   0x13, 0x74, 0x24, 0x00, 0xe3, 0x18, 0x04, 0xfc, 0x6f, 0xf0, 0xdf, 0xfd,
   0x23, 0x26, 0x00, 0x10, 0x73, 0x00, 0x10, 0x00, 0x73, 0x24, 0x20, 0x7b,
-  0x23, 0x22, 0x00, 0x10, 0x67, 0x00, 0x00, 0x30, 0x73, 0x24, 0x40, 0xf1,
-  0x23, 0x24, 0x80, 0x10, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b
+  0x23, 0x22, 0x00, 0x10, 0x0f, 0x00, 0xf0, 0x0f, 0x0f, 0x10, 0x00, 0x00,
+  0x67, 0x00, 0x00, 0x30, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x24, 0x80, 0x10,
+  0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b
 };
-static const unsigned int debug_rom_raw_len = 96;
+static const unsigned int debug_rom_raw_len = 104;