From: Andrew Waterman <andrew@sifive.com>
Date: Fri, 3 Nov 2017 02:15:42 +0000 (-0700)
Subject: Mask medeleg correctly
X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=95fafa8f05320a761f70bef022a05c3053ea7b27

Mask medeleg correctly
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 203394b..d23c1ea 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -360,9 +360,13 @@ void processor_t::set_csr(int which, reg_t val)
       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
       break;
     case CSR_MEDELEG: {
-      reg_t mask = CAUSE_MISALIGNED_FETCH | CAUSE_BREAKPOINT
-                 | CAUSE_USER_ECALL | CAUSE_FETCH_PAGE_FAULT
-                 | CAUSE_LOAD_PAGE_FAULT | CAUSE_STORE_PAGE_FAULT;
+      reg_t mask =
+        (1 << CAUSE_MISALIGNED_FETCH) |
+        (1 << CAUSE_BREAKPOINT) |
+        (1 << CAUSE_USER_ECALL) |
+        (1 << CAUSE_FETCH_PAGE_FAULT) |
+        (1 << CAUSE_LOAD_PAGE_FAULT) |
+        (1 << CAUSE_STORE_PAGE_FAULT);
       state.medeleg = (state.medeleg & ~mask) | (val & mask);
       break;
     }