From: Andrew Waterman Date: Tue, 6 Oct 2015 04:24:01 +0000 (-0700) Subject: more work towards RVC 1.8 X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=b0f3ed6e3bc78f11371864a0587d918c547b8022 more work towards RVC 1.8 --- diff --git a/riscv/decode.h b/riscv/decode.h index 2e3e542..5cb4ed3 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -79,16 +79,15 @@ public: int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); } int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); } int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); } - int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(5, 1) << 5) + (x(2, 3) << 6) + (xs(12, 1) << 9); } + int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(2, 1) << 5) + (x(5, 1) << 6) + (x(3, 2) << 7) + (xs(12, 1) << 9); } int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); } int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); } int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); } int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); } int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); } - int64_t rvc_lb_imm() { return (x(12, 1) + (x(5, 2) << 1) + (x(10, 2) << 3)); } int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); } - int64_t rvc_j_imm() { return (x(3, 4) << 1) + (x(2, 1) << 5) + (xs(7, 6) << 6); } - int64_t rvc_b_imm() { return (x(3, 4) << 1) + (x(2, 1) << 5) + (xs(10, 3) << 6); } + int64_t rvc_j_imm() { return (x(3, 3) << 1) + (x(11, 1) << 4) + (x(2, 1) << 5) + (x(7, 1) << 6) + (x(6, 1) << 7) + (x(9, 2) << 8) + (x(8, 1) << 10) + (xs(12, 1) << 11); } + int64_t rvc_b_imm() { return (x(3, 2) << 1) + (x(10, 2) << 3) + (x(2, 1) << 5) + (x(5, 2) << 6) + (xs(12, 1) << 8); } int64_t rvc_simm3() { return x(10, 3); } uint64_t rvc_rd() { return rd(); } uint64_t rvc_rs1() { return rd(); } diff --git a/riscv/encoding.h b/riscv/encoding.h index 5e8b122..5be3bdb 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -485,7 +485,7 @@ #define MASK_FNMADD_D 0x600007f #define MATCH_C_NOP 0x8001 #define MASK_C_NOP 0xffff -#define MATCH_C_ADDI16SP 0xe001 +#define MATCH_C_ADDI16SP 0xe101 #define MASK_C_ADDI16SP 0xef83 #define MATCH_C_JR 0x8002 #define MASK_C_JR 0xf07f @@ -493,32 +493,30 @@ #define MASK_C_JALR 0xf07f #define MATCH_C_EBREAK 0x9002 #define MASK_C_EBREAK 0xffff -#define MATCH_C_SD 0x6000 -#define MASK_C_SD 0xe003 -#define MATCH_C_LD 0xe000 +#define MATCH_C_LD 0x6000 #define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 #define MATCH_C_ADDIW 0xa001 #define MASK_C_ADDIW 0xe003 -#define MATCH_C_SDSP 0x6002 -#define MASK_C_SDSP 0xe003 -#define MATCH_C_LDSP 0xe002 +#define MATCH_C_LDSP 0x6002 #define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 #define MATCH_C_ADDI4SPN 0x0 #define MASK_C_ADDI4SPN 0xe003 -#define MATCH_C_FSD 0x2000 -#define MASK_C_FSD 0xe003 -#define MATCH_C_SW 0x4000 -#define MASK_C_SW 0xe003 -#define MATCH_C_FSW 0x6000 -#define MASK_C_FSW 0xe003 -#define MATCH_C_LBU 0x8000 -#define MASK_C_LBU 0xe003 -#define MATCH_C_FLD 0xa000 +#define MATCH_C_FLD 0x2000 #define MASK_C_FLD 0xe003 -#define MATCH_C_LW 0xc000 +#define MATCH_C_LW 0x4000 #define MASK_C_LW 0xe003 -#define MATCH_C_FLW 0xe000 +#define MATCH_C_FLW 0x6000 #define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 #define MATCH_C_SRLI 0x1 #define MASK_C_SRLI 0xec03 #define MATCH_C_SRAI 0x401 @@ -557,22 +555,22 @@ #define MASK_C_LUI 0xe003 #define MATCH_C_SLLI 0x2 #define MASK_C_SLLI 0xe003 -#define MATCH_C_FSDSP 0x2002 -#define MASK_C_FSDSP 0xe003 -#define MATCH_C_SWSP 0x4002 -#define MASK_C_SWSP 0xe003 -#define MATCH_C_FSWSP 0x6002 -#define MASK_C_FSWSP 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 #define MATCH_C_MV 0x8002 #define MASK_C_MV 0xf003 #define MATCH_C_ADD 0x9002 #define MASK_C_ADD 0xf003 -#define MATCH_C_FLDSP 0xa002 -#define MASK_C_FLDSP 0xe003 -#define MATCH_C_LWSP 0xc002 -#define MASK_C_LWSP 0xe003 -#define MATCH_C_FLWSP 0xe002 -#define MASK_C_FLWSP 0xe003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 #define CSR_FFLAGS 0x1 #define CSR_FRM 0x2 #define CSR_FCSR 0x3 @@ -820,19 +818,18 @@ DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) -DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) -DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -DECLARE_INSN(c_lbu, MATCH_C_LBU, MASK_C_LBU) DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) @@ -852,14 +849,14 @@ DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) -DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) -DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) -DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) #endif #ifdef DECLARE_CSR DECLARE_CSR(fflags, CSR_FFLAGS) diff --git a/riscv/insns/c_addi16sp.h b/riscv/insns/c_addi16sp.h deleted file mode 100644 index 3bc88a4..0000000 --- a/riscv/insns/c_addi16sp.h +++ /dev/null @@ -1,3 +0,0 @@ -require_extension('C'); -require(insn.rvc_addi16sp_imm() != 0); -WRITE_REG(X_SP, sext_xlen(RVC_SP + insn.rvc_addi16sp_imm())); diff --git a/riscv/insns/c_lbu.h b/riscv/insns/c_lbu.h deleted file mode 100644 index 74a03b9..0000000 --- a/riscv/insns/c_lbu.h +++ /dev/null @@ -1,2 +0,0 @@ -require_extension('C'); -WRITE_RVC_RS2S(MMU.load_uint8(RVC_RS1S + insn.rvc_lb_imm())); diff --git a/riscv/insns/c_lui.h b/riscv/insns/c_lui.h index e5060a3..130aaed 100644 --- a/riscv/insns/c_lui.h +++ b/riscv/insns/c_lui.h @@ -1,3 +1,8 @@ require_extension('C'); -require(insn.rvc_rd() != 0); -WRITE_RD(insn.rvc_imm() << 12); +if (insn.rvc_rd() == 2) { // c.addi16sp + require(insn.rvc_addi16sp_imm() != 0); + WRITE_REG(X_SP, sext_xlen(RVC_SP + insn.rvc_addi16sp_imm())); +} else { + require(insn.rvc_rd() != 0); + WRITE_RD(insn.rvc_imm() << 12); +} diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 882f34d..239beb9 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -81,7 +81,6 @@ riscv_insn_list = \ bltu \ bne \ c_add \ - c_addi16sp \ c_addi4spn \ c_addi \ c_addw \ @@ -104,7 +103,6 @@ riscv_insn_list = \ c_jr \ c_li \ c_lui \ - c_lbu \ c_lw \ c_lwsp \ c_mv \ diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc index 2bd9b6a..974d70e 100644 --- a/spike_main/disasm.cc +++ b/spike_main/disasm.cc @@ -22,7 +22,7 @@ struct : public arg_t { struct : public arg_t { std::string to_string(insn_t insn) const { - return std::string("0(") + xpr_name[insn.rs1()] + ')'; + return std::string("(") + xpr_name[insn.rs1()] + ')'; } } amo_address; @@ -212,12 +212,6 @@ struct : public arg_t { } } rvc_sdsp_address; -struct : public arg_t { - std::string to_string(insn_t insn) const { - return std::to_string((int)insn.rvc_lb_imm()) + '(' + xpr_name[insn.rvc_rs1s()] + ')'; - } -} rvc_lb_address; - struct : public arg_t { std::string to_string(insn_t insn) const { return std::to_string((int)insn.rvc_lw_imm()) + '(' + xpr_name[insn.rvc_rs1s()] + ')'; @@ -503,7 +497,7 @@ disassembler_t::disassembler_t() DISASM_INSN("jr", c_li, mask_rvc_imm, {&rvc_rs1}); DISASM_INSN("jalr", c_lui, mask_rvc_imm, {&rvc_rs1}); DISASM_INSN("nop", c_addi, mask_rd | mask_rvc_imm, {}); - DISASM_INSN("addi", c_addi, mask_rd, {&rvc_sp, &rvc_sp, &rvc_addi16sp_imm}); + DISASM_INSN("addi", c_addi16sp, mask_rd, {&rvc_sp, &rvc_sp, &rvc_addi16sp_imm}); DISASM_INSN("addi", c_addi4spn, 0, {&rvc_rs1s, &rvc_sp, &rvc_addi4spn_imm}); DISASM_INSN("li", c_li, 0, {&xrd, &rvc_imm}); DISASM_INSN("lui", c_lui, 0, {&xrd, &rvc_uimm}); @@ -524,7 +518,6 @@ disassembler_t::disassembler_t() DISASM_INSN("flw", c_flwsp, 0, {&xrd, &rvc_lwsp_address}); DISASM_INSN("sw", c_swsp, 0, {&rvc_rs2, &rvc_swsp_address}); DISASM_INSN("fsw", c_fswsp, 0, {&rvc_rs2, &rvc_swsp_address}); - DISASM_INSN("lbu", c_lbu, 0, {&rvc_rs2s, &rvc_lb_address}); DISASM_INSN("lw", c_lw, 0, {&rvc_rs2s, &rvc_lw_address}); DISASM_INSN("flw", c_flw, 0, {&rvc_rs2s, &rvc_lw_address}); DISASM_INSN("sw", c_sw, 0, {&rvc_rs2s, &rvc_lw_address});