From: Megan Wachs <megan@sifive.com>
Date: Mon, 17 Apr 2017 21:11:43 +0000 (-0700)
Subject: debug: Compiles again with new debug_defines.h file, but not tested.
X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=bbbe41e6365732a489d76b3bac5f5fafd0208482

debug: Compiles again with new debug_defines.h file, but not tested.
---

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 43dc737..7b113ab 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -369,16 +369,10 @@ bool debug_module_t::perform_abstract_command()
       write32(debug_rom_code, 1, ebreak());
     }
 
-    if (get_field(command, AC_ACCESS_REGISTER_PREEXEC)) {
-      write32(debug_rom_entry, dmcontrol.hartsel,
-          jal(ZERO, DEBUG_RAM_START - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel)));
-      next_action =
-        jal(ZERO, DEBUG_ROM_CODE - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel));
-    } else {
-      write32(debug_rom_entry, dmcontrol.hartsel,
-          jal(ZERO, DEBUG_ROM_CODE - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel)));
-    }
-
+    //TODO: Consider 'transfer' bit.
+    write32(debug_rom_entry, dmcontrol.hartsel,
+            jal(ZERO, DEBUG_ROM_CODE - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel)));
+    
     write32(debug_rom_exception, dmcontrol.hartsel,
         jal(ZERO, (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel) - DEBUG_ROM_EXCEPTION));
     abstractcs.busy = true;
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 9cd8f4d..40054cf 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -45,9 +45,7 @@ riscv_srcs = \
 	regnames.cc \
 	devices.cc \
 	rom.cc \
-	rtc.cc \
 	clint.cc \
-	gdbserver.cc \
 	debug_module.cc \
 	remote_bitbang.cc \
 	jtag_dtm.cc \