From: Shubhodeep Roy Choudhury <deepsrc@gmail.com>
Date: Fri, 16 Mar 2018 08:16:20 +0000 (+0530)
Subject: Fix for issue #183: No illegal instruction exception for c.sxxi instructions encoded... 
X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=be0555d585b332fd0496affe559c0a5a4e7e5644;hp=7e35a2a62f7433060e2ab1c98b3afd8b8a69b829

Fix for issue #183: No illegal instruction exception for c.sxxi instructions encoded with zero shift amount
---

diff --git a/riscv/insns/c_slli.h b/riscv/insns/c_slli.h
index 24fbb13..19d7908 100644
--- a/riscv/insns/c_slli.h
+++ b/riscv/insns/c_slli.h
@@ -1,3 +1,3 @@
 require_extension('C');
-require(insn.rvc_zimm() < xlen);
+require(insn.rvc_zimm() < xlen && insn.rvc_zimm() > 0);
 WRITE_RD(sext_xlen(RVC_RS1 << insn.rvc_zimm()));
diff --git a/riscv/insns/c_srai.h b/riscv/insns/c_srai.h
index f6638b1..7b594e9 100644
--- a/riscv/insns/c_srai.h
+++ b/riscv/insns/c_srai.h
@@ -1,3 +1,3 @@
 require_extension('C');
-require(insn.rvc_zimm() < xlen);
+require(insn.rvc_zimm() < xlen && insn.rvc_zimm() > 0);
 WRITE_RVC_RS1S(sext_xlen(sext_xlen(RVC_RS1S) >> insn.rvc_zimm()));
diff --git a/riscv/insns/c_srli.h b/riscv/insns/c_srli.h
index f410fef..008ae62 100644
--- a/riscv/insns/c_srli.h
+++ b/riscv/insns/c_srli.h
@@ -1,3 +1,3 @@
 require_extension('C');
-require(insn.rvc_zimm() < xlen);
+require(insn.rvc_zimm() < xlen && insn.rvc_zimm() > 0);
 WRITE_RVC_RS1S(sext_xlen(zext_xlen(RVC_RS1S) >> insn.rvc_zimm()));