From: Tim Newsome <tim@sifive.com>
Date: Thu, 21 Sep 2017 18:48:31 +0000 (-0700)
Subject: Fix comment typo. (#126)
X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=c471f5d84e2fc27e3eb4c2997635d3f2c83d7818

Fix comment typo. (#126)
---

diff --git a/riscv/execute.cc b/riscv/execute.cc
index 303effe..41425d9 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -154,7 +154,7 @@ void processor_t::step(size_t n)
         // This figures out where to jump to in the switch statement
         size_t idx = _mmu->icache_index(pc);
 
-        // This gets the cached decoded instruction form the MMU. If the MMU
+        // This gets the cached decoded instruction from the MMU. If the MMU
         // does not have the current pc cached, it will refill the MMU and
         // return the correct entry. ic_entry->data.func is the C++ function
         // corresponding to the instruction.