From: Tim Newsome <tim@sifive.com>
Date: Mon, 19 Feb 2018 19:55:19 +0000 (-0800)
Subject: Merge pull request #171 from riscv/sysbusbits
X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=c746388b542eacd2586acfbc0a742b08a5c0bd6f;hp=b2672e5d5271b346a71ec33ab42c88437b9b60d1

Merge pull request #171 from riscv/sysbusbits

Add support for debug bus mastering
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 516a708..8cca490 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -565,6 +565,11 @@ reg_t processor_t::get_csr(int which)
     case CSR_MINSTRET:
     case CSR_MCYCLE:
       return state.minstret;
+    case CSR_INSTRETH:
+    case CSR_CYCLEH:
+      if (ctr_ok && xlen == 32)
+        return state.minstret >> 32;
+      break;
     case CSR_MINSTRETH:
     case CSR_MCYCLEH:
       if (xlen == 32)