From: Tim Newsome <tim@sifive.com>
Date: Sat, 18 Feb 2017 02:50:44 +0000 (-0800)
Subject: Compress log output of jump-to-self loops.
X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=e36bacd9bce9ebf570d5e8bc5883b9a5190dcb9e

Compress log output of jump-to-self loops.

This helps hugely when reading "spike -l" output when debugging is going
on.
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 064c452..13aeaa4 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -270,9 +270,23 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
 
 void processor_t::disasm(insn_t insn)
 {
+  static uint64_t last_pc = 1, last_bits;
+  static uint64_t executions = 1;
+
   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
-  fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
-          id, state.pc, bits, disassembler->disassemble(insn).c_str());
+  if (last_pc != state.pc || last_bits != bits) {
+    if (executions != 1) {
+      fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
+    }
+
+    fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
+            id, state.pc, bits, disassembler->disassemble(insn).c_str());
+    last_pc = state.pc;
+    last_bits = bits;
+    executions = 1;
+  } else {
+    executions++;
+  }
 }
 
 static bool validate_vm(int max_xlen, reg_t vm)