From: Andrew Waterman <aswaterman@gmail.com>
Date: Mon, 5 Jan 2015 01:30:40 +0000 (-0800)
Subject: Disassemble jalr x0, x1, 0 as ret
X-Git-Url: https://git.libre-soc.org/?p=riscv-isa-sim.git;a=commitdiff_plain;h=f971129cb6f6f097f47b74eb3ce9b1872d6d253a

Disassemble jalr x0, x1, 0 as ret
---

diff --git a/spike_main/disasm.cc b/spike_main/disasm.cc
index 8fb1db8..10bd204 100644
--- a/spike_main/disasm.cc
+++ b/spike_main/disasm.cc
@@ -228,9 +228,9 @@ disassembler_t::disassembler_t()
   DEFINE_LTYPE(lui);
   DEFINE_LTYPE(auipc);
 
+  add_insn(new disasm_insn_t("ret", match_jalr | match_rs1_ra, mask_jalr | mask_rd | mask_rs1 | mask_imm, {}));
   DEFINE_I2TYPE("jr", jalr);
   add_insn(new disasm_insn_t("jalr", match_jalr | match_rd_ra, mask_jalr | mask_rd | mask_imm, {&xrs1}));
-  add_insn(new disasm_insn_t("ret", match_jalr | match_rs1_ra, mask_jalr | mask_rd | mask_rs1 | mask_imm, {}));
   DEFINE_ITYPE(jalr);
 
   add_insn(new disasm_insn_t("nop", match_addi, mask_addi | mask_rd | mask_rs1 | mask_imm, {}));