riscv-isa-sim.git
14 months agoUpdate README master
Andrew Waterman [Thu, 13 Sep 2018 06:56:49 +0000 (23:56 -0700)]
Update README

14 months agoMerge pull request #235 from riscv/sba
Tim Newsome [Thu, 6 Sep 2018 19:04:52 +0000 (12:04 -0700)]
Merge pull request #235 from riscv/sba

Fix cut-and-paste bug in 64-bit SBA loads.

14 months agoFix cut-and-paste bug in 64-bit SBA loads.
Tim Newsome [Wed, 5 Sep 2018 20:27:58 +0000 (13:27 -0700)]
Fix cut-and-paste bug in 64-bit SBA loads.

Fixes #234.

14 months agoHandle spike-dasm inputs with leading 0x correctly
Andrew Waterman [Fri, 24 Aug 2018 19:15:03 +0000 (12:15 -0700)]
Handle spike-dasm inputs with leading 0x correctly

14 months agoAdd dummy custom debug registers, to test OpenOCD. (#233)
Tim Newsome [Fri, 24 Aug 2018 03:36:41 +0000 (20:36 -0700)]
Add dummy custom debug registers, to test OpenOCD. (#233)

14 months agoFix several disassembler bugs
Andrew Waterman [Fri, 24 Aug 2018 00:17:17 +0000 (17:17 -0700)]
Fix several disassembler bugs

h/t Shane Lardinois

14 months agoAdd --disable-dtb option to suppress writing the DTB to memory
Andrew Waterman [Thu, 23 Aug 2018 23:54:36 +0000 (16:54 -0700)]
Add --disable-dtb option to suppress writing the DTB to memory

14 months agoMake IRQ_COP read-only/undelegable unless coprocessor is present
Andrew Waterman [Wed, 22 Aug 2018 21:07:45 +0000 (14:07 -0700)]
Make IRQ_COP read-only/undelegable unless coprocessor is present

14 months agoInstantiate disassembler after max_xlen is known
Andrew Waterman [Tue, 21 Aug 2018 21:24:23 +0000 (14:24 -0700)]
Instantiate disassembler after max_xlen is known

This fixes RVC disassembly.

It's done in a way that doesn't break 2cd60b277e909a5599ca48e4561cbfbc61460186

15 months agoDon't increment instret immediately after it is written (#231)
Andrew Waterman [Sat, 18 Aug 2018 01:49:47 +0000 (18:49 -0700)]
Don't increment instret immediately after it is written (#231)

This brings Spike into compliance with this clause in the spec:
https://github.com/riscv/riscv-isa-manual/blob/master/src/csr.tex#L96

15 months agoFix 2 trigger corner cases. (#229)
Tim Newsome [Fri, 10 Aug 2018 21:55:28 +0000 (14:55 -0700)]
Fix 2 trigger corner cases. (#229)

1. When hitting a trigger during a single step, dcsr.cause must reflect
the trigger not the step.
2. Also check for triggers on accesses that require a slow path fetch.

15 months agoMake sstatus.MXR readable
Andrew Waterman [Tue, 31 Jul 2018 18:26:47 +0000 (11:26 -0700)]
Make sstatus.MXR readable

h/t @taoliug

15 months agoFix using the uninitialized disassemble object. (#220)
SeungRyeol Lee [Mon, 23 Jul 2018 20:14:05 +0000 (05:14 +0900)]
Fix using the uninitialized disassemble object. (#220)

This fixes runtime crash when custom extension registers its
disassembly.

16 months agoRefactor and fix LR/SC implementation (#217)
Andrew Waterman [Tue, 10 Jul 2018 16:56:32 +0000 (09:56 -0700)]
Refactor and fix LR/SC implementation (#217)

- Use physical addresses to avoid homonym ambiguity (closes #215)

- Yield reservation on store-conditional (https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612)

- Don't yield reservation on exceptions (it's no longer required).

17 months agoMerge pull request #212 from riscv/hartsel
Tim Newsome [Tue, 12 Jun 2018 00:45:07 +0000 (17:45 -0700)]
Merge pull request #212 from riscv/hartsel

Update debug_defines.h

17 months agoUpdate debug_defines.h
Tim Newsome [Mon, 11 Jun 2018 20:36:30 +0000 (13:36 -0700)]
Update debug_defines.h

Add support for hartselhi parsing, but other parts of the debug code
still don't support more than 1024 harts.

17 months agoPut simif_t declaration in its own file. (#209)
Andy Wright [Thu, 31 May 2018 17:53:12 +0000 (13:53 -0400)]
Put simif_t declaration in its own file. (#209)

By separating the simif_t declaration from the sim_t declaration, the
simif_t declaration no longer depends on fesvr header files. This
simplifies compilation of custom sim class implementations that don't
depend on fesvr.

18 months agoFix install of missed header. (#207)
Prashanth Mundkur [Fri, 18 May 2018 20:45:35 +0000 (13:45 -0700)]
Fix install of missed header. (#207)

18 months agoExtract out device-tree generation and compilation into an exported api. (#197)
Prashanth Mundkur [Fri, 18 May 2018 20:38:57 +0000 (13:38 -0700)]
Extract out device-tree generation and compilation into an exported api. (#197)

18 months agoRevert "C.LWSP and C.LDSP with rd=0 are legal instructions"
Andrew Waterman [Fri, 4 May 2018 19:05:33 +0000 (12:05 -0700)]
Revert "C.LWSP and C.LDSP with rd=0 are legal instructions"

See https://github.com/riscv/riscv-isa-manual/commit/01190b6ebeb29cfac6783a3e7ce30cd529bf6c59

18 months agoC.LWSP and C.LDSP with rd=0 are legal instructions
Andrew Waterman [Fri, 4 May 2018 00:14:28 +0000 (17:14 -0700)]
C.LWSP and C.LDSP with rd=0 are legal instructions

This mistake derives from an ambiguity in the specification that has since been corrected: https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982

18 months agoFix commit log for serializing instructions
Andrew Waterman [Tue, 1 May 2018 03:20:43 +0000 (20:20 -0700)]
Fix commit log for serializing instructions

Resolves #199

18 months agoOnly break out of the simulator loop on WFI, not on CSR writes
Andrew Waterman [Mon, 30 Apr 2018 22:06:52 +0000 (15:06 -0700)]
Only break out of the simulator loop on WFI, not on CSR writes

Breaking out of the loop on WFI was intended to let other threads run
when the current thread has no work to do.  There's no advantage to doing
so on CSR writes, and the unintentional change in thread interleaving
broke some test programs that relied on short timer periods.

18 months agoWhen no arguments are passed, print spike help, not fesvr help
Andrew Waterman [Sun, 29 Apr 2018 07:41:42 +0000 (00:41 -0700)]
When no arguments are passed, print spike help, not fesvr help

19 months agoAllow querying the mmu configuration chosen during the build. (#191)
Prashanth Mundkur [Thu, 5 Apr 2018 00:25:01 +0000 (17:25 -0700)]
Allow querying the mmu configuration chosen during the build. (#191)

19 months agoRevert "Fix for issue #183: No illegal instruction exception for c.sxxi instructions...
Andrew Waterman [Wed, 4 Apr 2018 20:00:29 +0000 (13:00 -0700)]
Revert "Fix for issue #183: No illegal instruction exception for c.sxxi instructions encoded with zero shift amount"

This reverts commit be0555d585b332fd0496affe559c0a5a4e7e5644.

See #190

19 months agoMerge pull request #189 from pmundkur/pm-csr-name-api
Palmer Dabbelt [Fri, 30 Mar 2018 16:59:06 +0000 (09:59 -0700)]
Merge pull request #189 from pmundkur/pm-csr-name-api

Add an api to get the name for a CSR.

19 months agoAdd an api to get the name for a CSR.
Prashanth Mundkur [Mon, 26 Mar 2018 19:07:03 +0000 (12:07 -0700)]
Add an api to get the name for a CSR.

19 months agoImplement Hauser misa.C misalignment proposal (#187)
Andrew Waterman [Thu, 22 Mar 2018 00:19:16 +0000 (17:19 -0700)]
Implement Hauser misa.C misalignment proposal (#187)

See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7

- Reads of xEPC[1] are masked when RVC is disabled
- Writes to MISA are suppressed if they would cause a misaligned fetch
- Misaligned PCs no longer need to be checked upon fetch

19 months agoFix the access exception during page-table walks to match the original access type...
Prashanth Mundkur [Wed, 21 Mar 2018 20:24:51 +0000 (13:24 -0700)]
Fix the access exception during page-table walks to match the original access type, as specified in the manual. (#185)

20 months agoFix spike-dasm. (#184)
Tim Newsome [Mon, 19 Mar 2018 20:10:06 +0000 (13:10 -0700)]
Fix spike-dasm. (#184)

It had been broken by 90bafe660b323250338fd564bb9ab4316576d59b.

20 months agoMerge pull request #182 from riscv/reset_bits
Tim Newsome [Mon, 19 Mar 2018 16:35:55 +0000 (09:35 -0700)]
Merge pull request #182 from riscv/reset_bits

Implement debug havereset bits

20 months agoImplement debug havereset bits
Tim Newsome [Fri, 16 Mar 2018 21:52:09 +0000 (14:52 -0700)]
Implement debug havereset bits

20 months agoMerge branch 'deepsrc-b_fix_issue183'
Andrew Waterman [Fri, 16 Mar 2018 17:08:47 +0000 (10:08 -0700)]
Merge branch 'deepsrc-b_fix_issue183'

20 months agoFix for issue #183: No illegal instruction exception for c.sxxi instructions encoded...
Shubhodeep Roy Choudhury [Fri, 16 Mar 2018 08:16:20 +0000 (13:46 +0530)]
Fix for issue #183: No illegal instruction exception for c.sxxi instructions encoded with zero shift amount

20 months agoFix a bug caused by moving misa into state_t. (#180)
Prashanth Mundkur [Wed, 14 Mar 2018 16:48:11 +0000 (09:48 -0700)]
Fix a bug caused by moving misa into state_t. (#180)

* Fix misa losing its value in processor constructor due to state:reset() following state.misa initialization.
Make state:reset() preserve misa.

* Set state.misa to max_isa on reset().

* Idiomatic fix for earlier commit.

20 months agoMove processor.isa to state.misa, since it really belongs there.
Prashanth Mundkur [Tue, 13 Mar 2018 23:32:41 +0000 (16:32 -0700)]
Move processor.isa to state.misa, since it really belongs there.

20 months agoFix single stepping csrrw instructions (#178)
Tim Newsome [Sat, 10 Mar 2018 01:54:07 +0000 (17:54 -0800)]
Fix single stepping csrrw instructions (#178)

This code is still a bit voodoo to me, but now we pass all the tests
again. (Stepping was broken by
4299874ad4b07ef457776513a64e5b2397a6a75e.)

20 months agoMerge pull request #177 from riscv/debug_auth
Tim Newsome [Thu, 8 Mar 2018 01:17:39 +0000 (17:17 -0800)]
Merge pull request #177 from riscv/debug_auth

Add debug module authentication.

20 months agoNarrow the interface used by the processors and memory to the top-level simulator...
Prashanth Mundkur [Tue, 20 Feb 2018 23:16:53 +0000 (15:16 -0800)]
Narrow the interface used by the processors and memory to the top-level simulator/htif.
This allows the implementation of an alternative top-level simulator class.

20 months agoFix install of a missed header from debug_rom.
Prashanth Mundkur [Mon, 26 Feb 2018 23:37:01 +0000 (15:37 -0800)]
Fix install of a missed header from debug_rom.

The installed header files from the riscv subproject were incomplete, since
processor.h includes debug_rom_defines.h, and the latter was not installed.
Fix by moving it into riscv/, add it to the riscv subproject header list, which
ensures it will get installed.  While here, also add a missed dependency of debug_rom
on riscv/encoding.h to debug_rom/Makefile.

20 months agoFix a missed header file in the softfloat include install.
Prashanth Mundkur [Mon, 26 Feb 2018 23:21:27 +0000 (15:21 -0800)]
Fix a missed header file in the softfloat include install.

20 months agoImplement clearing-misa.C-while-PC-is-misaligned proposal
Andrew Waterman [Thu, 22 Feb 2018 23:19:26 +0000 (15:19 -0800)]
Implement clearing-misa.C-while-PC-is-misaligned proposal

See https://github.com/riscv/riscv-isa-manual/pull/139

Not adopted yet, but I'm putting the implementation here for reference.

20 months agoEnforce 2-byte alignment of mepc/sepc/dpc
Andrew Waterman [Thu, 22 Feb 2018 00:09:31 +0000 (16:09 -0800)]
Enforce 2-byte alignment of mepc/sepc/dpc

20 months agoMerge pull request #173 from riscv/no_progbuf3
Tim Newsome [Thu, 1 Mar 2018 23:18:01 +0000 (15:18 -0800)]
Merge pull request #173 from riscv/no_progbuf3

Add support for abstract debug access to CSRs and FPRs

20 months agoAdd debug module authentication.
Tim Newsome [Tue, 27 Feb 2018 20:30:46 +0000 (12:30 -0800)]
Add debug module authentication.

Off by default, enabled with --debug-auth.
The protocol is very simple (definitely not secure) to allow debuggers
to test their authentication feature. To authenticate a debugger must:
1. Read authdata
2. Write to authdata the value that it just read, plus 1

20 months agoDon't allow 32-bit instructions to take up multiple slots in I$
Andrew Waterman [Wed, 21 Feb 2018 21:25:44 +0000 (13:25 -0800)]
Don't allow 32-bit instructions to take up multiple slots in I$

I$ indices now maintain a 1:N relationship with PCs.  This is somewhat
faster and also simpler.

20 months agoMerge pull request #171 from riscv/sysbusbits
Tim Newsome [Mon, 19 Feb 2018 19:55:19 +0000 (11:55 -0800)]
Merge pull request #171 from riscv/sysbusbits

Add support for debug bus mastering

20 months agoPasses smoke tests with --progsize=0
Tim Newsome [Tue, 30 Jan 2018 22:13:23 +0000 (14:13 -0800)]
Passes smoke tests with --progsize=0

20 months agoWIP. Doesn't work.
Tim Newsome [Tue, 30 Jan 2018 20:19:55 +0000 (12:19 -0800)]
WIP. Doesn't work.

21 months agoImplement cycleh/instreth CSRs for RV32 (#172)
Andrew Waterman [Tue, 13 Feb 2018 18:43:36 +0000 (10:43 -0800)]
Implement cycleh/instreth CSRs for RV32 (#172)

21 months agoAdd --debug-sba option
Tim Newsome [Thu, 1 Feb 2018 22:32:00 +0000 (14:32 -0800)]
Add --debug-sba option

This lets the user control whether the system bus access implements bus
mastering.

21 months agoUpdate debug_defines
Tim Newsome [Mon, 29 Jan 2018 19:52:31 +0000 (11:52 -0800)]
Update debug_defines

22 months agoSupport debug system bus access.
Tim Newsome [Fri, 12 Jan 2018 23:26:00 +0000 (15:26 -0800)]
Support debug system bus access.

22 months agoUse new debug_defines.h.
Tim Newsome [Tue, 9 Jan 2018 20:29:34 +0000 (12:29 -0800)]
Use new debug_defines.h.

22 months agomem_t: Throw an error if zero-sized memory is requested (#168)
Jonathan Neuschäfer [Tue, 9 Jan 2018 00:00:55 +0000 (01:00 +0100)]
mem_t: Throw an error if zero-sized memory is requested (#168)

* mem_t: Throw an error if zero-sized memory is requested

If for some reason the user requests a memory size of 0 megabytes, print
a useful error message.

* Check for overflow in memory size

If the user passes in a large enough memory size (-m) that the size in
bytes doesn't fit into size_t, catch this error in the make_mems function.

22 months agoAdd some missing RVC instructions to disassembler
Andrew Waterman [Wed, 3 Jan 2018 21:06:21 +0000 (13:06 -0800)]
Add some missing RVC instructions to disassembler

23 months agoMerge pull request #165 from riscv/small_progbuf
Tim Newsome [Mon, 18 Dec 2017 22:25:42 +0000 (14:25 -0800)]
Merge pull request #165 from riscv/small_progbuf

Add support for program buffer of size 2

23 months agoUpdate debug_defines to latest version.
Tim Newsome [Mon, 11 Dec 2017 22:28:10 +0000 (14:28 -0800)]
Update debug_defines to latest version.

23 months agoSet impebreak.
Tim Newsome [Thu, 12 Oct 2017 19:07:11 +0000 (12:07 -0700)]
Set impebreak.

23 months agoUpdate to latest debug_defines.h.
Tim Newsome [Thu, 12 Oct 2017 19:05:26 +0000 (12:05 -0700)]
Update to latest debug_defines.h.

23 months agoMake progbuf a run-time option.
Tim Newsome [Tue, 10 Oct 2017 22:53:23 +0000 (15:53 -0700)]
Make progbuf a run-time option.

Also add an implicit ebreak after the program buffer. This is not part
of the spec, but hopefully it will be.

23 months agoRename badaddr to tval
Andrew Waterman [Mon, 27 Nov 2017 22:29:03 +0000 (14:29 -0800)]
Rename badaddr to tval

23 months agoRename sptbr to satp
Andrew Waterman [Mon, 27 Nov 2017 22:28:29 +0000 (14:28 -0800)]
Rename sptbr to satp

23 months agoSet tval to 0 on traps with no specified tval
Andrew Waterman [Mon, 27 Nov 2017 22:18:06 +0000 (14:18 -0800)]
Set tval to 0 on traps with no specified tval

Simply not writing the register was not a conformant implementation.

23 months agoImplement priv-1.11 interrupt-priority scheme (#161)
Andrew Waterman [Mon, 20 Nov 2017 19:58:14 +0000 (11:58 -0800)]
Implement priv-1.11 interrupt-priority scheme (#161)

Closes #159.

https://github.com/riscv/riscv-isa-manual/commit/a62e76cb16eb508199f74632eb8bf263739f25a3

23 months agoFix commitlog. (#162)
Christopher Celio [Mon, 20 Nov 2017 19:41:31 +0000 (11:41 -0800)]
Fix commitlog. (#162)

A regression caused any instruction with rd=x0 to not be emitted.

2 years agoMerge pull request #156 from p12nGH/noncontiguous_harts
Andrew Waterman [Thu, 16 Nov 2017 00:17:40 +0000 (16:17 -0800)]
Merge pull request #156 from p12nGH/noncontiguous_harts

Support for non-contiguous hartids

2 years agohartids knob description added
Gleb Gagarin [Wed, 15 Nov 2017 23:42:39 +0000 (15:42 -0800)]
hartids knob description added

2 years agoSupport for non-contiguous hartids
Gleb Gagarin [Wed, 15 Nov 2017 23:35:59 +0000 (15:35 -0800)]
Support for non-contiguous hartids

2 years agoRemove redundant U/S mode advertisement
Andrew Waterman [Fri, 10 Nov 2017 03:27:20 +0000 (19:27 -0800)]
Remove redundant U/S mode advertisement

2 years agoH-mode no longer exists
Andrew Waterman [Fri, 10 Nov 2017 02:46:27 +0000 (18:46 -0800)]
H-mode no longer exists

It's supplanted by the hypervisor extension, which doesn't use the privilege
encoding of 2; it still looks like supervisor (i.e. 1).

2 years agoMPP is now WARL
Andrew Waterman [Fri, 10 Nov 2017 02:45:48 +0000 (18:45 -0800)]
MPP is now WARL

2 years agoImplement Q extension for disassembler (#153)
Kito Cheng [Mon, 6 Nov 2017 20:16:50 +0000 (04:16 +0800)]
Implement Q extension for disassembler (#153)

2 years agoFix disassembly of c.li 0
Andrew Waterman [Sat, 4 Nov 2017 01:13:22 +0000 (18:13 -0700)]
Fix disassembly of c.li 0

Resolves #152

2 years agoMerge pull request #151 from riscv/htif_dts
Palmer Dabbelt [Fri, 3 Nov 2017 23:29:57 +0000 (16:29 -0700)]
Merge pull request #151 from riscv/htif_dts

Put HTIF in the device tree

2 years agoPut HTIF in the device tree
Palmer Dabbelt [Fri, 3 Nov 2017 22:38:12 +0000 (15:38 -0700)]
Put HTIF in the device tree

I wanted to actually put the address of the HTIF into the DTS, but that
seems to be a bit too much work: since the HTIF addresses are just
defined in an ELF file it's a bit awkward to make that work.

Instead, I'm just putting a dummy HTIF key in the DTS.

2 years agoMask medeleg correctly
Andrew Waterman [Fri, 3 Nov 2017 02:15:42 +0000 (19:15 -0700)]
Mask medeleg correctly

2 years agoDon't permit delegation of interrupts that M-mode should handle
Andrew Waterman [Thu, 2 Nov 2017 01:57:02 +0000 (18:57 -0700)]
Don't permit delegation of interrupts that M-mode should handle

2 years agoFix commit-log for Q extension, and for RV32 (#143)
Andrew Waterman [Fri, 20 Oct 2017 04:07:22 +0000 (00:07 -0400)]
Fix commit-log for Q extension, and for RV32 (#143)

* Fix commit-log for Q extension, and for RV32

The number of nibbles printed out now depends upon XLEN or FLEN,
as appropriate.

* Factor out FLEN calculation

2 years agoFix bus_t bug with devices at 0x0
Evan Cox [Thu, 19 Oct 2017 16:40:10 +0000 (11:40 -0500)]
Fix bus_t bug with devices at 0x0

Fix a bug that prevented bus_t from storing to, loading from,
or finding a device that existed at address 0x0.

Resolves: #135

2 years agoFix implementation of FMIN/FMAX NaN case
Andrew Waterman [Thu, 19 Oct 2017 19:18:23 +0000 (12:18 -0700)]
Fix implementation of FMIN/FMAX NaN case

If rd=rs1 or rd=rs2, the NaN check examined the wrong value.

2 years agoInclude math.h for NAN (#137)
jar [Sun, 15 Oct 2017 18:22:45 +0000 (14:22 -0400)]
Include math.h for NAN (#137)

commit 85c40db208db3e26f507dc6a74a5dc540b504b5c introduced a NAN dependency but did not include the math.h header

2 years agoMerge pull request #129 from riscv/q-extension
Andrew Waterman [Wed, 11 Oct 2017 01:17:58 +0000 (18:17 -0700)]
Merge pull request #129 from riscv/q-extension

Implement Q extension

2 years agoImplement Q extension
Andrew Waterman [Mon, 25 Sep 2017 03:34:04 +0000 (20:34 -0700)]
Implement Q extension

2 years agoMerge pull request #128 from riscv/reset
Tim Newsome [Mon, 25 Sep 2017 18:05:36 +0000 (11:05 -0700)]
Merge pull request #128 from riscv/reset

Fix debug reset.

2 years agoUpdate SoftFloat
Andrew Waterman [Mon, 25 Sep 2017 03:25:34 +0000 (20:25 -0700)]
Update SoftFloat

2 years agoActually let hartreset be set.
Tim Newsome [Thu, 21 Sep 2017 21:54:06 +0000 (14:54 -0700)]
Actually let hartreset be set.

2 years agoFix debug reset.
Tim Newsome [Thu, 21 Sep 2017 19:34:42 +0000 (12:34 -0700)]
Fix debug reset.

ndmreset now resets all harts (instead of just the current hart), and
hartreset resets the selected hart (instead of being ignored).

2 years agoFix corner case in repeated execution (#127)
Tim Newsome [Thu, 21 Sep 2017 19:42:20 +0000 (12:42 -0700)]
Fix corner case in repeated execution (#127)

Specifically, don't print out the execution count if the same
instruction is executed by different harts.

2 years agoFix comment typo. (#126)
Tim Newsome [Thu, 21 Sep 2017 18:48:31 +0000 (11:48 -0700)]
Fix comment typo. (#126)

2 years agoMerge pull request #123 from riscv/debug_interrupts
Tim Newsome [Tue, 12 Sep 2017 20:53:17 +0000 (13:53 -0700)]
Merge pull request #123 from riscv/debug_interrupts

Don't take interrupts while in Debug Mode.

2 years agoDon't take interrupts while in Debug Mode.
Tim Newsome [Tue, 12 Sep 2017 18:04:08 +0000 (11:04 -0700)]
Don't take interrupts while in Debug Mode.

2 years agoMerge pull request #121 from riscv/debug_store
Tim Newsome [Mon, 28 Aug 2017 22:46:08 +0000 (15:46 -0700)]
Merge pull request #121 from riscv/debug_store

Add a nice debug printf for debug_module_t::store

2 years agoAdd a nice debug printf for debug_module_t::store
Tim Newsome [Mon, 28 Aug 2017 22:19:41 +0000 (15:19 -0700)]
Add a nice debug printf for debug_module_t::store

2 years agoMerge pull request #119 from riscv/quiet
Tim Newsome [Fri, 11 Aug 2017 22:48:15 +0000 (15:48 -0700)]
Merge pull request #119 from riscv/quiet

Turn off debug module debug printfs.

2 years agoTurn off debug module debug printfs.
Tim Newsome [Fri, 11 Aug 2017 22:35:22 +0000 (15:35 -0700)]
Turn off debug module debug printfs.

Nobody wants to see all that, and if they do they should recompile.

2 years agoCorrect c.li and c.lui disassembly (#118)
Palmer Dabbelt [Thu, 10 Aug 2017 22:50:30 +0000 (15:50 -0700)]
Correct c.li and c.lui disassembly (#118)

I currently get this disassembly

    00004881 jr      a7

but if I understand that's incorrect and I want

    00004881 li      a7, 0

If I'm reading the ISA manual correctly, the disassembler was just wrong
here.

2 years agoMerge pull request #117 from riscv/multicore_debug
Tim Newsome [Thu, 10 Aug 2017 20:44:42 +0000 (13:44 -0700)]
Merge pull request #117 from riscv/multicore_debug

Fix multicore debug.

2 years agoFix multicore debug.
Tim Newsome [Mon, 7 Aug 2017 18:21:58 +0000 (11:21 -0700)]
Fix multicore debug.

In an older implementation I was thinking of having different entry
points for different harts, but that's no longer true.

Also get rid of a bunch of trailing whitespace.