From 3d17e24e8d82f6e69df86fb8960b0e7b4bc5f30d Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Fri, 13 Jun 2014 03:52:48 -0700 Subject: [PATCH] Commit log now prints while interrupts are enabled. - Previous behavior was to print the commit log only in user code. --- riscv/decode.h | 8 ++------ riscv/processor.cc | 23 +++++++++++++++-------- 2 files changed, 17 insertions(+), 14 deletions(-) diff --git a/riscv/decode.h b/riscv/decode.h index 4c3d274..ce57c77 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -101,10 +101,8 @@ private: #ifdef RISCV_ENABLE_COMMITLOG #undef WRITE_RD #define WRITE_RD(value) ({ \ - bool in_spvr = p->get_state()->sr & SR_S; \ reg_t wdata = value; /* value is a func with side-effects */ \ - if (!in_spvr) \ - p->get_state()->log_reg_write = (commit_log_reg_t){insn.rd() << 1, wdata}; \ + p->get_state()->log_reg_write = (commit_log_reg_t){insn.rd() << 1, wdata}; \ p->get_state()->XPR.write(insn.rd(), wdata); \ }) #endif @@ -117,10 +115,8 @@ private: #ifdef RISCV_ENABLE_COMMITLOG #undef WRITE_FRD #define WRITE_FRD(value) ({ \ - bool in_spvr = p->get_state()->sr & SR_S; \ freg_t wdata = value; /* value is a func with side-effects */ \ - if (!in_spvr) \ - p->get_state()->log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \ + p->get_state()->log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \ p->get_state()->FPR.write(insn.rd(), wdata); \ }) #endif diff --git a/riscv/processor.cc b/riscv/processor.cc index e40e65b..4e4c4ff 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -99,13 +99,19 @@ void processor_t::take_interrupt() static void commit_log(state_t* state, insn_t insn) { #ifdef RISCV_ENABLE_COMMITLOG - if (!(state->sr & SR_S)) { - fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", state->pc, insn.bits()); - if (state->log_reg_write.addr) - fprintf(stderr, "%c%02u 0x%016" PRIx64, state->log_reg_write.addr & 1 ? 'f' : 'x', + if (state->sr & SR_EI) { + if (state->log_reg_write.addr) { + fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx32 ") %c%2u 0x%016" PRIx64 "\n", + state->pc, insn.bits(), + state->log_reg_write.addr & 1 ? 'f' : 'x', state->log_reg_write.addr >> 1, state->log_reg_write.data); - state->log_reg_write.addr = 0; + } + else { + fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx32 ")\n", + state->pc, insn.bits()); + } } + state->log_reg_write.addr = 0; #endif } @@ -129,8 +135,9 @@ void processor_t::step(size_t n) { insn_fetch_t fetch = mmu->load_insn(state.pc); disasm(fetch.insn.insn); + reg_t npc = fetch.func(this, fetch.insn.insn, state.pc); commit_log(&state, fetch.insn.insn); - state.pc = fetch.func(this, fetch.insn.insn, state.pc); + state.pc = npc; } } else while (n > 0) @@ -142,9 +149,9 @@ void processor_t::step(size_t n) insn_t insn = ic_entry->data.insn.insn; \ insn_func_t func = ic_entry->data.func; \ ic_entry++; \ - reg_t pc = func(this, insn, state.pc); \ + reg_t npc = func(this, insn, state.pc); \ commit_log(&state, insn); \ - state.pc = pc; \ + state.pc = npc; \ if (idx < ICACHE_SIZE-1 && unlikely(ic_entry->tag != state.pc)) break; \ } -- 2.30.2