# Connect to a mult-icore RISC-V target, exposing each hart as a thread.
adapter_khz     10000

interface remote_bitbang
remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
remote_bitbang_port $::env(REMOTE_BITBANG_PORT)

set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913

set _TARGETNAME_0 $_CHIPNAME.cpu0
set _TARGETNAME_1 $_CHIPNAME.cpu1
target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0
target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1

gdb_report_data_abort enable

# Expose an unimplemented CSR so we can test non-existent register access
# behavior.
riscv expose_csrs 2288

init
reset halt