Test resuming from a trigger.

[riscv-tests.git] / debug / gdbserver.py

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index bf279503ecb41c921ec82695de213ebac45c9642..f0385d568441b3eeb8d1d73dc5f71b19b2a7d221 100755 (executable)
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -660,12 +660,17 @@ class TriggerLoadAddressInstant(TriggerTest):
         self.gdb.command("b just_before_read_loop")
         self.gdb.c()
         read_loop = self.gdb.p("&read_loop")
+        read_again = self.gdb.p("&read_again")
         self.gdb.command("rwatch data")
         self.gdb.c()
         # Accept hitting the breakpoint before or after the load instruction.
         assertIn(self.gdb.p("$pc"), [read_loop, read_loop + 4])
         assertEqual(self.gdb.p("$a0"), self.gdb.p("&data"))
 
+        self.gdb.c()
+        assertIn(self.gdb.p("$pc"), [read_again, read_again + 4])
+        assertEqual(self.gdb.p("$a0"), self.gdb.p("&data"))
+
 # FIXME: Triggers aren't quite working yet
 #class TriggerStoreAddress(TriggerTest):
 #    def test(self):
@@ -855,9 +860,13 @@ class PrivRw(PrivTest):
         """Test reading/writing priv."""
         # Disable physical memory protection by allowing U mode access to all
         # memory.
-        self.gdb.p("$pmpcfg0=0xf")  # TOR, R, W, X
-        self.gdb.p("$pmpaddr0=0x%x" %
-                ((self.hart.ram + self.hart.ram_size) >> 2))
+        try:
+            self.gdb.p("$pmpcfg0=0xf")  # TOR, R, W, X
+            self.gdb.p("$pmpaddr0=0x%x" %
+                    ((self.hart.ram + self.hart.ram_size) >> 2))
+        except testlib.CouldNotFetch:
+            # PMP registers are optional
+            pass
 
         # Leave the PC at _start, where the first 4 instructions should be
         # legal in any mode.