Tolerate missing misa register.

[riscv-tests.git] / debug / programs / entry.S

diff --git a/debug/programs/entry.S b/debug/programs/entry.S
index c9e319ccc0549b31d4ef148bfc2ca8c62e15556d..ff8ae3092a517ad20ce2860b7b56ac2d1cd05b5a 100755 (executable)
--- a/debug/programs/entry.S
+++ b/debug/programs/entry.S
@@ -27,7 +27,9 @@ trap_vector:
   j trap_entry
 
 handle_reset:
-  la t0, trap_entry
+  // If misa doesn't exist (or is following an old spec where it has a
+  // different number), skip the next block.
+  la t0, 3f
   csrw mtvec, t0
   csrwi mstatus, 0
 
@@ -48,6 +50,10 @@ handle_reset:
   csrwi medeleg, 0
 2:
   csrwi mie, 0
+3:
+  la t0, trap_entry
+  csrw mtvec, t0
+  csrwi mstatus, 0
 
   # initialize global pointer
 .option push