debug: Use consistent 'sim_cmd' argument.

[riscv-tests.git] / debug / targets.py

diff --git a/debug/targets.py b/debug/targets.py
index a69f43d91463924ccee841d7f9aaaac640710a7b..17e752df8e72fe71749842ab8afc2bc2102c151e 100644 (file)
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -127,7 +127,7 @@ class FreedomU500SimTarget(Target):
     openocd_config = "targets/%s/openocd.cfg" % name
 
     def target(self):
-        return testlib.VcsSim(simv=self.sim_cmd, debug=False)
+        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
 
 targets = [
         Spike32Target,