debug: checkpoint of trying to get simulation tests working

[riscv-tests.git] / debug / targets / HiFive1 / openocd.cfg

diff --git a/debug/targets/HiFive1/openocd.cfg b/debug/targets/HiFive1/openocd.cfg
index d2c2879358598def797d7766d3c581c655796f3c..72a54469d8664b936337d62c8b9eb9ff642d84ab 100644 (file)
--- a/debug/targets/HiFive1/openocd.cfg
+++ b/debug/targets/HiFive1/openocd.cfg
@@ -14,7 +14,7 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1 -rtos riscv
 
 flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
 init