Use `gdb_report_register_access_error enable`

[riscv-tests.git] / debug / targets / RISC-V / spike-1.cfg

diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg
index f420417dcd505e5d47c03040bef6a9dc4ada7c20..083794fc14906a9fd9b133810371ba373bc20fbe 100644 (file)
--- a/debug/targets/RISC-V/spike-1.cfg
+++ b/debug/targets/RISC-V/spike-1.cfg
@@ -11,6 +11,7 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 
 gdb_report_data_abort enable
+gdb_report_register_access_error enable
 
 # Expose an unimplemented CSR so we can test non-existent register access
 # behavior.