Test debug authentication.

[riscv-tests.git] / debug / targets / RISC-V / spike-2.cfg

diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg
index 17526eccda20beec185e228a06ab339104d99b36..114d5b880b953861066d045b20112535226c9477 100644 (file)
--- a/debug/targets/RISC-V/spike-2.cfg
+++ b/debug/targets/RISC-V/spike-2.cfg
@@ -15,5 +15,16 @@ target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
 
 gdb_report_data_abort enable
 
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+
 init
-reset halt
+
+set challenge [ocd_riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+targets $_TARGETNAME_0
+halt
+targets $_TARGETNAME_1
+halt