Use `gdb_report_register_access_error enable`

[riscv-tests.git] / debug / targets / RISC-V / spike-2.cfg

diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg
index 114d5b880b953861066d045b20112535226c9477..ef8bab10bff9d2c204638b60ab3f1065a5f100e1 100644 (file)
--- a/debug/targets/RISC-V/spike-2.cfg
+++ b/debug/targets/RISC-V/spike-2.cfg
@@ -14,6 +14,7 @@ target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0
 target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
 
 gdb_report_data_abort enable
+gdb_report_register_access_error enable
 
 # Expose an unimplemented CSR so we can test non-existent register access
 # behavior.