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Allow multiple reset vectors.
[riscv-tests.git] / debug / targets / RISC-V / spike64.py
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
index 6e3da896ef01b79a454893fe964def2da1c441ab..9c37f877e544f3d081e8d6b0578ed3125728ad45 100644 (file)
--- a/debug/targets/RISC-V/spike64.py
+++ b/debug/targets/RISC-V/spike64.py
@@ -6,7 +6,7 @@ class spike64_hart(targets.Hart):
     ram = 0x1212340000
     ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
-    reset_vector = 0x1000
+    reset_vectors = [0x1000]
     link_script_path = "spike64.lds"
 
 class spike64(targets.Target):