Make the debug tests aware of multicore.

[riscv-tests.git] / debug / targets / SiFive / Freedom / E300.py

diff --git a/debug/targets/SiFive/Freedom/E300.py b/debug/targets/SiFive/Freedom/E300.py
index 95ddcfd6273a598a6aecf52e0000b0aac8e8a514..170de400df202221b7834678bcb300d89f2ba10d 100644 (file)
--- a/debug/targets/SiFive/Freedom/E300.py
+++ b/debug/targets/SiFive/Freedom/E300.py
@@ -1,9 +1,12 @@
 import targets
 
-class E300(targets.Target):
+class E300Hart(targets.Hart):
     xlen = 32
     ram = 0x80000000
-    ram_size = 16 * 1024
+    ram_size = 256 * 1024 * 1024
     instruction_hardware_breakpoint_count = 2
-    openocd_config_path = "Freedom.cfg"
     link_script_path = "Freedom.lds"
+
+class E300(targets.Target):
+    openocd_config_path = "Freedom.cfg"
+    harts = [E300Hart()]