Make the debug tests aware of multicore.

[riscv-tests.git] / debug / targets / SiFive / Freedom / U500.py

diff --git a/debug/targets/SiFive/Freedom/U500.py b/debug/targets/SiFive/Freedom/U500.py
index c22aa4c6907fd3b280550e812f558dc05b627812..6da3ac509c5b53c7d75034983404b19159d6a945 100644 (file)
--- a/debug/targets/SiFive/Freedom/U500.py
+++ b/debug/targets/SiFive/Freedom/U500.py
@@ -1,9 +1,12 @@
 import targets
 
-class U500(targets.Target):
+class U500Hart(targets.Hart):
     xlen = 64
     ram = 0x80000000
     ram_size = 16 * 1024
     instruction_hardware_breakpoint_count = 2
-    openocd_config_path = "Freedom.cfg"
     link_script_path = "Freedom.lds"
+
+class U500(targets.Target):
+    openocd_config_path = "Freedom.cfg"
+    harts = [U500Hart()]