debug: checkpoint of trying to get simulation tests working

[riscv-tests.git] / debug / targets / freedom-e300-sim / openocd.cfg

diff --git a/debug/targets/freedom-e300-sim/openocd.cfg b/debug/targets/freedom-e300-sim/openocd.cfg
index f3d9cb43a596f8fd90263d0cfaebff33da5c2903..fcb8451daa505982eab588e9196b2cc118aecb26 100644 (file)
--- a/debug/targets/freedom-e300-sim/openocd.cfg
+++ b/debug/targets/freedom-e300-sim/openocd.cfg
@@ -2,6 +2,7 @@ adapter_khz     10000
 
 source [find interface/jtag_vpi.cfg]
 jtag_vpi_set_port $::env(JTAG_VPI_PORT)
+#jtag_vpi_set_port 34448
 
 set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
@@ -11,3 +12,4 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
 
 init
 halt
+echo "OK GO NOW"