debug: checkpoint of trying to get simulation tests working

[riscv-tests.git] / debug / targets / freedom-u500-sim / openocd.cfg

diff --git a/debug/targets/freedom-u500-sim/openocd.cfg b/debug/targets/freedom-u500-sim/openocd.cfg
index 9239c83ddde91c20de939040bee122b3ab03292a..0ce11d80eb4f96323b9237e99ade74a9ee223a27 100644 (file)
--- a/debug/targets/freedom-u500-sim/openocd.cfg
+++ b/debug/targets/freedom-u500-sim/openocd.cfg
@@ -1,8 +1,8 @@
 adapter_khz     10000
 
 source [find interface/jtag_vpi.cfg]
-jtag_vpi_set_port $::env(JTAG_VPI_PORT)
-#jtag_vpi_set_port 44005
+#jtag_vpi_set_port $::env(JTAG_VPI_PORT)
+jtag_vpi_set_port 46401
 
 set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913