debug: checkpoint of trying to get simulation tests working

[riscv-tests.git] / debug / targets / freedom-u500 / openocd.cfg

diff --git a/debug/targets/freedom-u500/openocd.cfg b/debug/targets/freedom-u500/openocd.cfg
index d448989243ecc7d893ed4eca399eb2d62b737c76..3e3bcad62a9a342cbc75174a4444e1b387a6fac4 100644 (file)
--- a/debug/targets/freedom-u500/openocd.cfg
+++ b/debug/targets/freedom-u500/openocd.cfg
@@ -6,7 +6,7 @@ set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
 
 init