debug: Use consistent 'sim_cmd' argument.

[riscv-tests.git] / debug / testlib.py

diff --git a/debug/testlib.py b/debug/testlib.py
index a66d59a7b450baf63e7b99aa6c50ef6e0ded3fec..df976df66ac1684ce85ae3e2d162e28c6cf567da 100644 (file)
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -113,7 +113,7 @@ class Spike(object):
 class VcsSim(object):
     def __init__(self, sim_cmd=None, debug=False):
         if sim_cmd:
-            cmd = shlex.split(simv)
+            cmd = shlex.split(sim_cmd)
         else:
             cmd = ["simv"]
         cmd += ["+jtag_vpi_enable"]