Reflect changes to ISA

[riscv-tests.git] / env / p / riscv_test.h

diff --git a/env/p/riscv_test.h b/env/p/riscv_test.h
index a537fb2494add1af1c8503476805c81c995d910d..08af9dc40ad12439ce70e8fd196fdf43191ccd0c 100644 (file)
--- a/env/p/riscv_test.h
+++ b/env/p/riscv_test.h
@@ -1,44 +1,81 @@
 #ifndef _ENV_PHYSICAL_SINGLE_CORE_H
 #define _ENV_PHYSICAL_SINGLE_CORE_H
 
+#include "../pcr.h"
+
 //-----------------------------------------------------------------------
 // Begin Macro
 //-----------------------------------------------------------------------
 
 #define RVTEST_RV64U                                                    \
+  .macro init;                                                          \
+  .endm
 
 #define RVTEST_RV64UF                                                   \
-  RVTEST_RV64U;                                                         \
-  RVTEST_FP_ENABLE
+  .macro init;                                                          \
+  RVTEST_FP_ENABLE;                                                     \
+  .endm
+
+#define RVTEST_RV64UV                                                   \
+  .macro init;                                                          \
+  RVTEST_FP_ENABLE;                                                     \
+  RVTEST_VEC_ENABLE;                                                    \
+  .endm
 
 #define RVTEST_RV32U                                                    \
-  clearpcr cr0, 0x80
+  .macro init;                                                          \
+  RVTEST_32_ENABLE;                                                     \
+  .endm
+
+#define RVTEST_RV32UF                                                   \
+  .macro init;                                                          \
+  RVTEST_32_ENABLE;                                                     \
+  RVTEST_FP_ENABLE;                                                     \
+  .endm
+
+#define RVTEST_RV32UV                                                   \
+  .macro init;                                                          \
+  RVTEST_32_ENABLE;                                                     \
+  RVTEST_FP_ENABLE;                                                     \
+  RVTEST_VEC_ENABLE;                                                    \
+  .endm
 
 #define RVTEST_RV64S                                                    \
+  .macro init;                                                          \
+  .endm
+
+#define RVTEST_32_ENABLE                                                \
+  clearpcr status, SR_S64                                               \
 
 #define RVTEST_FP_ENABLE                                                \
-  setpcr cr0, 2;                                                        \
-  mfpcr a0, cr0;                                                        \
-  and   a0, a0, 2;                                                      \
+  setpcr status, SR_EF;                                                 \
+  mfpcr a0, status;                                                     \
+  and   a0, a0, SR_EF;                                                  \
   bnez  a0, 2f;                                                         \
   RVTEST_PASS;                                                          \
-2:mtfsr x0;                                                             \
+2:fssr x0;                                                              \
 
 #define RVTEST_VEC_ENABLE                                               \
-  mfpcr a0, cr0;                                                        \
-  ori   a0, a0, 4;                                                      \
-  mtpcr a0, cr0;                                                        \
-  li    a0, 0xff;                                                       \
-  mtpcr a0, cr18;                                                       \
+  setpcr status, SR_EV;                                                 \
+  mfpcr a0, status;                                                     \
+  and   a0, a0, SR_EV;                                                  \
+  bnez  a0, 2f;                                                         \
+  RVTEST_PASS;                                                          \
+2:                                                                      \
+
+#define RISCV_MULTICORE_DISABLE                                         \
+        mfpcr a0, hartid; 1: bnez a0, 1b;                               \
+
+#define EXTRA_INIT
 
 #define RVTEST_CODE_BEGIN                                               \
         .text;                                                          \
         .align  4;                                                      \
         .global _start;                                                 \
 _start:                                                                 \
-        RVTEST_FP_ENABLE                                                \
-        RVTEST_VEC_ENABLE                                               \
-        mfpcr a0, cr10; 1: bnez a0, 1b;                                 \
+        RISCV_MULTICORE_DISABLE;                                        \
+        init;                                                           \
+        EXTRA_INIT;                                                     \
 
 //-----------------------------------------------------------------------
 // End Macro
@@ -53,7 +90,7 @@ _start:                                                                 \
 #define RVTEST_PASS                                                     \
         fence;                                                          \
         li  x1, 1;                                                      \
-        mtpcr x1, cr30;                                                 \
+        mtpcr x1, tohost;                                               \
 1:      b 1b;                                                           \
 
 #define RVTEST_FAIL                                                     \
@@ -61,16 +98,18 @@ _start:                                                                 \
         beqz x28, 1f;                                                   \
         sll x28, x28, 1;                                                \
         or x28, x28, 1;                                                 \
-        mtpcr x28, cr30;                                                \
+        mtpcr x28, tohost;                                              \
 1:      b 1b;                                                           \
 
 //-----------------------------------------------------------------------
 // Data Section Macro
 //-----------------------------------------------------------------------
 
-#define RVTEST_DATA_BEGIN
+#define RVTEST_DATA_BEGIN EXTRA_DATA
 #define RVTEST_DATA_END
 
+#define EXTRA_DATA
+
 //#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
 //#define RVTEST_DATA_END .align 4; .global end_signature; end_signature: