Reflect changes to ISA

[riscv-tests.git] / env / pm / riscv_test.h

diff --git a/env/pm/riscv_test.h b/env/pm/riscv_test.h
index 98d058044ff25384fc62f51b303838ffd657a5ef..4bd16372eb3682e9703ba04c21691d96d52a0645 100644 (file)
--- a/env/pm/riscv_test.h
+++ b/env/pm/riscv_test.h
@@ -1,73 +1,9 @@
 #ifndef _ENV_PHYSICAL_MULTI_CORE_H
-#define _ENV_PHYSICAL_MULTI_CORE_H
+#define _ENV_PHYSICAL_MULTI_CORE_HA
 
-//-----------------------------------------------------------------------
-// Begin Macro
-//-----------------------------------------------------------------------
+#include "../p/riscv_test.h"
 
-#define RVTEST_RV64U                                                    \
-
-#define RVTEST_RV64UF                                                   \
-  RVTEST_RV64U;                                                         \
-  RVTEST_FP_ENABLE
-
-#define RVTEST_RV64S                                                    \
-
-#define RVTEST_FP_ENABLE                                                \
-  setpcr cr0, 2;                                                        \
-  mfpcr a0, cr0;                                                        \
-  and   a0, a0, 2;                                                      \
-  bnez  a0, 2f;                                                         \
-  RVTEST_PASS;                                                          \
-2:mtfsr x0;                                                             \
-
-#define RVTEST_VEC_ENABLE                                               \
-  mfpcr a0, cr0;                                                        \
-  ori   a0, a0, 4;                                                      \
-  mtpcr a0, cr0;                                                        \
-  li    a0, 0xff;                                                       \
-  mtpcr a0, cr18;                                                       \
-
-#define RVTEST_CODE_BEGIN                                               \
-        .text;                                                          \
-        .align  4;                                                      \
-        .global _start;                                                 \
-_start:                                                                 \
-        RVTEST_FP_ENABLE                                                \
-        RVTEST_VEC_ENABLE                                               \
-
-//-----------------------------------------------------------------------
-// End Macro
-//-----------------------------------------------------------------------
-
-#define RVTEST_CODE_END                                                 \
-
-//-----------------------------------------------------------------------
-// Pass/Fail Macro
-//-----------------------------------------------------------------------
-
-#define RVTEST_FAIL                                                     \
-        fence;                                                          \
-        beqz x28, 1f;                                                   \
-        sll x28, x28, 1;                                                \
-        or x28, x28, 1;                                                 \
-        mtpcr x28, cr30;                                                \
-1:      b 1b;                                                           \
-
-#define RVTEST_PASS                                                     \
-        fence;                                                          \
-        li  x1, 1;                                                      \
-        mtpcr x1, cr30;                                                 \
-1:      b 1b;                                                           \
-
-//-----------------------------------------------------------------------
-// Data Section Macro
-//-----------------------------------------------------------------------
-
-#define RVTEST_DATA_BEGIN
-#define RVTEST_DATA_END
-
-//#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
-//#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
+#undef RISCV_MULTICORE_DISABLE
+#define RISCV_MULTICORE_DISABLE
 
 #endif