Updating test macro to take load instruction parameter

[riscv-tests.git] / isa / macros / simplev / sv_test_macros.h

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index 1c7977c87aa4690b6fb7f144f9773cfb846619d3..3d99af58cf2e4c2ac3bf12ca6275ea2f0bea151f 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -109,15 +109,15 @@
         fmv.x.s x2, freg; \
         bne     x2, x1, fail;
 
-#define SV_ELWIDTH_TEST(code, testdata, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+#define SV_ELWIDTH_TEST(code, load_instruction, testdata, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
                          expect1, expect2, expect3 )                   \
                                                                        \
-        SV_LDD_DATA( x12, testdata   , 0);                             \
-        SV_LDD_DATA( x13, testdata+8 , 0);                             \
-        SV_LDD_DATA( x14, testdata+16, 0);                             \
-        SV_LDD_DATA( x15, testdata+24, 0);                             \
-        SV_LDD_DATA( x16, testdata+32, 0);                             \
-        SV_LDD_DATA( x17, testdata+40, 0);                             \
+        load_instruction( x12, testdata   , 0);                             \
+        load_instruction( x13, testdata+8 , 0);                             \
+        load_instruction( x14, testdata+16, 0);                             \
+        load_instruction( x15, testdata+24, 0);                             \
+        load_instruction( x16, testdata+32, 0);                             \
+        load_instruction( x17, testdata+40, 0);                             \
                                                                                \
         li x28, 0xa5a5a5a5a5a5a5a5;                                     \
         li x29, 0xa5a5a5a5a5a5a5a5;                                     \