la x1, from; \
fld reg, offs(x1)
+#define SV_FLW_DATA( reg, from, offs ) \
+ la x1, from; \
+ flw reg, offs(x1)
+
#define TEST_SV_IMM( reg, imm ) \
li t6, ((imm) & 0xffffffffffffffff); \
bne reg, t6, fail
fmv.x.d x2, freg; \
bne x2, x1, fail
+#define TEST_SV_FW( flags, freg, from, offs ) \
+ fsflags x2, x0; \
+ li x1, flags; \
+ bne x2, x1, fail; \
+ la x1, from; \
+ lw x1, offs(x1); \
+ fmv.x.s x2, freg; \
+ bne x2, x1, fail
+
#define SV_W_DFLT 0
#define SV_W_8BIT 1
#define SV_W_16BIT 2