augment sv_addi test using macros

[riscv-tests.git] / isa / macros / simplev / sv_test_macros.h

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index fb26814644b9cf726ac118d7ab502f833ca395fd..d77287403e2c96b1a2b4c2c14773bed78751a4d4 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -1,4 +1,22 @@
-#define SV_REG_CSR(type, regkey, elwidth, regidx, isvec, packed) \
+#define SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ) \
   (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<14) | (packed<<15))
-#define SV_PRED_CSR(type, regkey, zero, inv, regidx, active) \
+
+#define SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \
   (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (active<<14))
+
+#define SET_SV_CSR( type, regkey, elwidth, regidx, isvec, packed ) \
+        li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ); \
+        csrrw  x0, 0x4c0, x1
+
+#define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
+
+#define SET_SV_MVL( val ) csrrwi   x0, 0x4f2, val
+#define SET_SV_VL( val )  csrrwi   x0, 0x4f0, val
+
+#define SV_LD_DATA( reg, from, offs ) \
+        la      x1, from; \
+        lw      reg, offs(x1)
+
+#define TEST_SV_IMM( reg, imm ) \
+        li      x1, imm; \
+        bne     reg, x1, fail