add extra mulh sv elwidth tests

[riscv-tests.git] / isa / macros / simplev / sv_test_macros.h

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index 18de70d98217ddc5fc7d0cbf3f89c3c1f0683202..f725de9e3561d74463ac30762fedbe9981f54e7f 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -77,11 +77,11 @@
 
 #define TEST_SV_IMMW( reg, imm ) \
         li      t6, MASK_XLEN(imm) ; \
-        bne     reg, t6, fail
+        bne     reg, t6, fail;
 
 #define TEST_SV_IMM( reg, imm ) \
         li      t6, ((imm) & 0xffffffffffffffff); \
-        bne     reg, t6, fail
+        bne     reg, t6, fail;
 
 #define TEST_SV_FD( flags, freg, from, offs ) \
         fsflags x2, x0; \
@@ -90,7 +90,7 @@
         la      x1, from; \
         ld      x1, offs(x1); \
         fmv.x.d x2, freg; \
-        bne     x2, x1, fail
+        bne     x2, x1, fail;
 
 #define TEST_SV_FW( flags, freg, from, offs ) \
         fsflags x2, x0; \
@@ -99,7 +99,7 @@
         la      x1, from; \
         lw      x1, offs(x1); \
         fmv.x.s x2, freg; \
-        bne     x2, x1, fail
+        bne     x2, x1, fail;
 
 #define SV_W_DFLT 0
 #define SV_W_8BIT 1