Check mtval in rv64mi-p-illegal (#104)

[riscv-tests.git] / isa / rv64mi / illegal.S

diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S
index 30105e68d61df08741e14d560e35fb736bb150e3..d825c44927124ecb6c3cf15757c53c91cfd31bb3 100644 (file)
--- a/isa/rv64mi/illegal.S
+++ b/isa/rv64mi/illegal.S
@@ -21,6 +21,15 @@ bad2:
   .word 0
   j fail
 
+  # Skip the rest of the test if S-mode is not present.
+  li t0, MSTATUS_MPP
+  csrc mstatus, t0
+  li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
+  csrs mstatus, t1
+  csrr t2, mstatus
+  and t2, t2, t0
+  bne t1, t2, pass
+
   # Test vectored interrupts if they are supported.
 test_vectored_interrupts:
   csrwi mip, MIP_SSIP
@@ -33,23 +42,18 @@ test_vectored_interrupts:
   csrsi mstatus, MSTATUS_MIE
 1:
   j 1b
-
 msip:
   csrw mtvec, s0
 
-  # Skip the rest of the test if S-mode is not present.
-  li t0, MSTATUS_MPP
-  csrc mstatus, t0
-  li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
-  csrs mstatus, t1
-  csrr t2, mstatus
-  and t2, t2, t0
-  bne t1, t2, pass
-
   # Delegate supervisor software interrupts so WFI won't stall.
   csrwi mideleg, MIP_SSIP
+  # Enter supervisor mode.
   la t0, 1f
   csrw mepc, t0
+  li t0, MSTATUS_MPP
+  csrc mstatus, t0
+  li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
+  csrs mstatus, t1
   mret
 
 1:
@@ -102,6 +106,7 @@ bad9:
   TEST_PASSFAIL
 
   .align 8
+  .global mtvec_handler
 mtvec_handler:
   j synchronous_exception
   j msip
@@ -125,6 +130,17 @@ synchronous_exception:
   csrr t0, mcause
   bne t0, t1, fail
   csrr t0, mepc
+
+  # Make sure mtval contains either 0 or the instruction word.
+  csrr t2, mbadaddr
+  beqz t2, 1f
+  lhu t3, 0(t0)
+  lhu t4, 2(t0)
+  slli t4, t4, 16
+  or t3, t3, t4
+  bne t2, t3, fail
+1:
+
   la t1, bad2
   beq t0, t1, 2f
   la t1, bad3