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Check mtval in rv64mi-p-illegal (#104)
[riscv-tests.git]
/
isa
/
rv64mi
/
illegal.S
diff --git
a/isa/rv64mi/illegal.S
b/isa/rv64mi/illegal.S
index 3bb7961596d095735ff1d3ec2233479fd43cf8de..d825c44927124ecb6c3cf15757c53c91cfd31bb3 100644
(file)
--- a/
isa/rv64mi/illegal.S
+++ b/
isa/rv64mi/illegal.S
@@
-130,6
+130,17
@@
synchronous_exception:
csrr t0, mcause
bne t0, t1, fail
csrr t0, mepc
csrr t0, mcause
bne t0, t1, fail
csrr t0, mepc
+
+ # Make sure mtval contains either 0 or the instruction word.
+ csrr t2, mbadaddr
+ beqz t2, 1f
+ lhu t3, 0(t0)
+ lhu t4, 2(t0)
+ slli t4, t4, 16
+ or t3, t3, t4
+ bne t2, t3, fail
+1:
+
la t1, bad2
beq t0, t1, 2f
la t1, bad3
la t1, bad2
beq t0, t1, 2f
la t1, bad3