Check mtval in rv64mi-p-illegal (#104)

[riscv-tests.git] / isa / rv64mi / illegal.S

diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S
index a1b445f0df08c7b3b47ab9b9fe41d62f4e115d08..d825c44927124ecb6c3cf15757c53c91cfd31bb3 100644 (file)
--- a/isa/rv64mi/illegal.S
+++ b/isa/rv64mi/illegal.S
@@ -106,6 +106,7 @@ bad9:
   TEST_PASSFAIL
 
   .align 8
+  .global mtvec_handler
 mtvec_handler:
   j synchronous_exception
   j msip
@@ -129,6 +130,17 @@ synchronous_exception:
   csrr t0, mcause
   bne t0, t1, fail
   csrr t0, mepc
+
+  # Make sure mtval contains either 0 or the instruction word.
+  csrr t2, mbadaddr
+  beqz t2, 1f
+  lhu t3, 0(t0)
+  lhu t4, 2(t0)
+  slli t4, t4, 16
+  or t3, t3, t4
+  bne t2, t3, fail
+1:
+
   la t1, bad2
   beq t0, t1, 2f
   la t1, bad3