Update to new breakpoint & counter spec

[riscv-tests.git] / isa / rv64si / csr.S

diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index 68f6fb109abce94c67cfff1c33e3d979b6be0bb5..1f7bb7722a7b1a840c36118a03795bf23eac943e 100644 (file)
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -42,12 +42,6 @@ RVTEST_CODE_BEGIN
   beqz a0, finish # if no user mode, skip the rest of these checks
 #endif
 
-  # Make sure writing the cycle counter causes an exception.
-  # Don't run in supervisor, as we don't delegate illegal instruction traps.
-#ifdef __MACHINE_MODE
-  TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0);
-#endif
-
   # jump to user land
   li t0, SSTATUS_SPP
   csrc sstatus, t0
@@ -56,6 +50,12 @@ RVTEST_CODE_BEGIN
   sret
   1:
 
+  # Make sure writing the cycle counter causes an exception.
+  # Don't run in supervisor, as we don't delegate illegal instruction traps.
+#ifdef __MACHINE_MODE
+  TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0);
+#endif
+
   # Make sure reading status in user mode causes an exception.
   # Don't run in supervisor, as we don't delegate illegal instruction traps.
 #ifdef __MACHINE_MODE