Reflect changes to ISA

[riscv-tests.git] / isa / rv64si / ipi.S

diff --git a/isa/rv64si/ipi.S b/isa/rv64si/ipi.S
index 92ae14960ce6e0b8daf5f291403aa21430d82072..8db016369aeb87aac96c959c7f501e25c2d5b72d 100644 (file)
--- a/isa/rv64si/ipi.S
+++ b/isa/rv64si/ipi.S
@@ -13,12 +13,12 @@ RVTEST_CODE_BEGIN
 
   # clear pending IPIs then enable interrupts
   la a0, handler
-  mtpcr a0, cr3
-  mtpcr x0, cr9
-  mfpcr a0, cr0
-  li a1, 0x00ff0001
+  mtpcr a0, evec
+  mtpcr x0, clear_ipi
+  mfpcr a0, status
+  li a1, SR_EI | (1 << (IRQ_IPI + SR_IM_SHIFT))
   or a0, a0, a1
-  mtpcr a0, cr0
+  mtpcr a0, status
 
   # wait for all cores to boot
   la a0, coreid
@@ -29,15 +29,15 @@ RVTEST_CODE_BEGIN
   blt a1, a3, 1b
 
   # IPI dominoes
-  mfpcr a0, cr10
+  mfpcr a0, hartid
   1: bnez a0, 1b
   add a0, a0, 1
   rem a0, a0, a3
-  mtpcr a0, cr8
+  mtpcr a0, send_ipi
   1: b 1b
 
   handler:
-  mfpcr a0, cr10
+  mfpcr a0, hartid
   bnez a0, 2f
   RVTEST_PASS
 
@@ -45,7 +45,7 @@ RVTEST_CODE_BEGIN
 
   2: add a0, a0, 1
   rem a0, a0, a3
-  mtpcr a0, cr8
+  mtpcr a0, send_ipi
   1: b 1b
 
 RVTEST_CODE_END