whoops overwrote x2

[riscv-tests.git] / isa / rv64uc / sv_c_mv.S

diff --git a/isa/rv64uc/sv_c_mv.S b/isa/rv64uc/sv_c_mv.S
index a10d33c5508763640a491ba3f55798c4f5033122..c85108ce8c548a2ece7836996343760af14ccace 100644 (file)
--- a/isa/rv64uc/sv_c_mv.S
+++ b/isa/rv64uc/sv_c_mv.S
@@ -14,30 +14,30 @@ RVTEST_CODE_BEGIN   # Start of test code.
 
         .option norvc
 
-        SV_LD_DATA( x5, testdata+0 , 0)
-        SV_LD_DATA( x6, testdata+8, 0)
-        SV_LD_DATA( x7, testdata+16, 0)
+        SV_LD_DATA( x6, testdata+0 , 0)
+        SV_LD_DATA( x7, testdata+8, 0)
+        SV_LD_DATA( x8, testdata+16, 0)
 
-        li          x2, 0 # deliberately set x3 to 0 (target of add)
-        li          x3, 0 # deliberately set x4 to 0
+        li          x3, 0 # deliberately set x3 to 0 (target of add)
         li          x4, 0 # deliberately set x4 to 0
+        li          x5, 0 # deliberately set x4 to 0
 
         SET_SV_MVL(3)
-        SET_SV_2CSRS( SV_REG_CSR(1, 2, 0, 2, 1, 0),
-                      SV_REG_CSR(1, 5, 0, 5, 1, 0) )
+        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1, 0),
+                      SV_REG_CSR(1, 6, 0, 6, 1, 0) )
         SET_SV_VL(3)
 
         .option rvc
-        c.mv    x2, x5
+        c.mv    x3, x6
         .option norvc
 
         SET_SV_VL(0)
         CLR_SV_CSRS()
         SET_SV_MVL(0)
 
-        TEST_SV_IMM(x2, 1001) # should not be modified
-        TEST_SV_IMM(x3, 41)
-        TEST_SV_IMM(x4, 42)
+        TEST_SV_IMM(x3, 1001) # should not be modified
+        TEST_SV_IMM(x4, 41)
+        TEST_SV_IMM(x5, 42)
 
         RVTEST_PASS           # Signal success.
 fail: