whoops overwrote x2

[riscv-tests.git] / isa / rv64uc / sv_c_mv_predication.S

diff --git a/isa/rv64uc/sv_c_mv_predication.S b/isa/rv64uc/sv_c_mv_predication.S
index 65b2bd6c4c732f028725a90f9d36b6f9910ec9eb..3ad6535f586584b10151d5eda959632a066241a7 100644 (file)
--- a/isa/rv64uc/sv_c_mv_predication.S
+++ b/isa/rv64uc/sv_c_mv_predication.S
@@ -6,35 +6,35 @@ RVTEST_RV64U        # Define TVM used by program.
 
 #define SV_PRED_C_MV_TEST( pred1, pred2, expect1, expect2, expect3 ) \
                                                        \
-        SV_LD_DATA( x5, testdata+0 , 0);               \
-        SV_LD_DATA( x6, testdata+8, 0);                \
-        SV_LD_DATA( x7, testdata+16, 0);               \
+        SV_LD_DATA( x6, testdata+0 , 0);               \
+        SV_LD_DATA( x7, testdata+8, 0);                \
+        SV_LD_DATA( x8, testdata+16, 0);               \
                                                        \
-        li          x2, 2;                             \
-        li          x3, 3;                             \
-        li          x4, 4;                             \
+        li          x3, 2;                             \
+        li          x4, 3;                             \
+        li          x5, 4;                             \
         li          a3, pred1;                         \
         li          a4, pred2;                         \
                                                        \
         SET_SV_MVL(3);                                 \
-        SET_SV_2CSRS( SV_REG_CSR(1, 2, 0, 2, 1, 0),    \
-                      SV_REG_CSR(1, 5, 0, 5, 1, 0) );  \
+        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1, 0),    \
+                      SV_REG_CSR(1, 6, 0, 6, 1, 0) );  \
         SET_SV_2PREDCSRS(                              \
-                      SV_PRED_CSR(1, 2, 0, 0, 13, 1),  \
-                      SV_PRED_CSR(1, 5, 0, 0, 14, 1) );\
+                      SV_PRED_CSR(1, 3, 0, 0, 13, 1),  \
+                      SV_PRED_CSR(1, 6, 0, 0, 14, 1) );\
         SET_SV_VL(3);                                  \
                                                        \
         .option rvc;                                   \
-        c.mv    x2, x5;                                \
+        c.mv    x3, x6;                                \
         .option norvc;                                 \
                                                        \
         SET_SV_VL(0);                                  \
         CLR_SV_CSRS();                                 \
         SET_SV_MVL(0);                                 \
                                                        \
-        TEST_SV_IMM(x2, expect1);                      \
-        TEST_SV_IMM(x3, expect2);                      \
-        TEST_SV_IMM(x4, expect3);
+        TEST_SV_IMM(x3, expect1);                      \
+        TEST_SV_IMM(x4, expect2);                      \
+        TEST_SV_IMM(x5, expect3);
 
 # SV test: vector-vector add different rd and rs1
 #