update sv test comments

[riscv-tests.git] / isa / rv64ui / sv_addi.S

diff --git a/isa/rv64ui/sv_addi.S b/isa/rv64ui/sv_addi.S
index e86a3f36c6a91f64ba1a38a3121c4d25e77a89fd..123052cf02e1e9e42764f9cef9881783b660d028 100644 (file)
--- a/isa/rv64ui/sv_addi.S
+++ b/isa/rv64ui/sv_addi.S
@@ -4,7 +4,9 @@
 RVTEST_RV64U        # Define TVM used by program.
 
 
-# SV test: sets up x3 and x4 with data, sets VL to 2, and carries out
+# SV test: vector-vector add
+#
+# sets up x3 and x4 with data, sets VL to 2, and carries out
 # an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
 
 # Test code region.