update sv test comments

[riscv-tests.git] / isa / rv64ui / sv_addi_redirect.S

diff --git a/isa/rv64ui/sv_addi_redirect.S b/isa/rv64ui/sv_addi_redirect.S
index 980cb5b4c483f924c6adda9e0397da471f2ccbef..61e92842147e295fc91295caa98997e06a3d9cb3 100644 (file)
--- a/isa/rv64ui/sv_addi_redirect.S
+++ b/isa/rv64ui/sv_addi_redirect.S
@@ -3,7 +3,9 @@
 
 RVTEST_RV64U        # Define TVM used by program.
 
-# SV test: sets up x3 and x4 with data, then sets up SV redirection
+# SV test: vector-vector (redirected) add
+#
+# sets up x3 and x4 with data, then sets up SV redirection
 # from register x16 to register x3 with a VL of 2.  the add is carried out
 # on x16 and the redirection means "actually, we want to do that add on x3"
 # and the VL means "actually we want to do that add on x3 *AND* x4"