X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=debug%2Fgdbserver.py;h=8c500bcf80109b8f051d32d1130e0f4fcdebe5d6;hp=bf279503ecb41c921ec82695de213ebac45c9642;hb=6d97e25f4da3e92dee131b1836184836ef280b26;hpb=c2e2e06836b597d983c98f33a7ea38e8e4889935

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index bf27950..8c500bc 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -855,9 +855,13 @@ class PrivRw(PrivTest):
         """Test reading/writing priv."""
         # Disable physical memory protection by allowing U mode access to all
         # memory.
-        self.gdb.p("$pmpcfg0=0xf")  # TOR, R, W, X
-        self.gdb.p("$pmpaddr0=0x%x" %
-                ((self.hart.ram + self.hart.ram_size) >> 2))
+        try:
+            self.gdb.p("$pmpcfg0=0xf")  # TOR, R, W, X
+            self.gdb.p("$pmpaddr0=0x%x" %
+                    ((self.hart.ram + self.hart.ram_size) >> 2))
+        except testlib.CouldNotFetch:
+            # PMP registers are optional
+            pass
 
         # Leave the PC at _start, where the first 4 instructions should be
         # legal in any mode.