X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=debug%2Fprograms%2Ftrigger.S;h=13f044978c830ecf31e72dfecc14503ccf4ef7db;hp=3d502dc45887e4fdcf56b8857b0a680283d8d789;hb=ba39c5fc2885eb1400d6f9e13ae6c7588c1c1241;hpb=1637fcbfd1b25b7341767ab7caa7a8173f471a51

diff --git a/debug/programs/trigger.S b/debug/programs/trigger.S
index 3d502dc..13f0449 100644
--- a/debug/programs/trigger.S
+++ b/debug/programs/trigger.S
@@ -8,16 +8,6 @@
 # define LREG lw
 # define SREG sw
 # define REGBYTES 4
-#endif
-
-#undef MCONTROL_TYPE
-#undef MCONTROL_DMODE
-#if __riscv_xlen == 64
-# define MCONTROL_TYPE    (0xf<<(64-4))
-# define MCONTROL_DMODE   (1<<(64-5))
-#else
-# define MCONTROL_TYPE    (0xf<<(32-4))
-# define MCONTROL_DMODE   (1<<(32-5))
 #endif
 
         .global         main
@@ -31,7 +21,10 @@ just_before_read_loop:
         li      t2, 16
 read_loop:
         lw      t1, 0(a0)
+        addi    t1, t1, 1
         addi    t0, t0, 1
+read_again:
+        lw      t1, 0(a0)
         addi    a0, a0, 4
         blt     t0, t2, read_loop