X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=debug%2Ftargets%2FRISC-V%2Fspike-rtos.cfg;h=d8bd27e903aa333b4bf7b5d2cf970fd367404b64;hp=159a70fac42c7ffcaa6af1f1371ef43f0f73fdce;hb=4ab18e0f8e6381f0a16e8b812d4ee202e9465192;hpb=45380af7d42ee3302fc229030694f8ea4506d79f

diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg
index 159a70f..d8bd27e 100644
--- a/debug/targets/RISC-V/spike-rtos.cfg
+++ b/debug/targets/RISC-V/spike-rtos.cfg
@@ -12,6 +12,7 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
 
 gdb_report_data_abort enable
+gdb_report_register_access_error enable
 
 # Expose an unimplemented CSR so we can test non-existent register access
 # behavior.